{"id":399568,"date":"2024-10-20T04:43:48","date_gmt":"2024-10-20T04:43:48","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1394-2008-2\/"},"modified":"2024-10-26T08:32:00","modified_gmt":"2024-10-26T08:32:00","slug":"ieee-1394-2008-2","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1394-2008-2\/","title":{"rendered":"IEEE 1394-2008"},"content":{"rendered":"

Revision Standard – Active. This standard provides specifications for a high-speed serial bus that supports both asynchronous and isochronous communication and integrates well with most IEEE standard 32-bit and 64-bit parallel buses. It is intended to provide a low-cost interconnect between cards on the same backplane, cards on other backplanes, and external peripherals. Interfaces to longer distance transmission media [such as unshielded twisted pair (UTP), optical fiber, and plastic optical fiber (POF)] allow the interconnection to be extended throughout a local network. This standard follows the command and status register (CSR) architecture of IEEE Std 1212-2001.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Standard for a High-Performance Serial Bus <\/td>\n<\/tr>\n
3<\/td>\nTitle page <\/td>\n<\/tr>\n
6<\/td>\nIntroduction
Notice to users
Laws and regulations
Copyrights
Updating of IEEE documents
Errata <\/td>\n<\/tr>\n
7<\/td>\nInterpretations
Patents
Participants <\/td>\n<\/tr>\n
11<\/td>\nContents <\/td>\n<\/tr>\n
33<\/td>\nList of figures <\/td>\n<\/tr>\n
41<\/td>\nList of tables <\/td>\n<\/tr>\n
49<\/td>\nImportand notice
1. Overview
1.1 Scope and purpose
1.1.1 Scope <\/td>\n<\/tr>\n
50<\/td>\n1.1.2 Purpose
1.2 Document organization
1.3 Serial bus applications
1.3.1 Alternate bus
1.3.2 Low-cost peripheral bus <\/td>\n<\/tr>\n
51<\/td>\n1.3.3 Bus bridge
1.4 Service model <\/td>\n<\/tr>\n
52<\/td>\n1.5 Document notation
1.5.1 Mechanical notation
1.5.2 Signal naming
1.5.3 Size notation <\/td>\n<\/tr>\n
53<\/td>\n1.5.4 Numerical values <\/td>\n<\/tr>\n
54<\/td>\n1.5.5 Packet formats
1.5.6 Register formats
1.5.7 C code notation <\/td>\n<\/tr>\n
56<\/td>\n1.5.8 State machine notation
1.5.9 CSR, ROM, and field notation <\/td>\n<\/tr>\n
57<\/td>\n1.5.10 Register specification format <\/td>\n<\/tr>\n
58<\/td>\n1.5.11 Reserved registers and fields <\/td>\n<\/tr>\n
59<\/td>\n1.5.12 Operation description priorities
1.6 Compliance
1.6.1 CSR architecture compliance <\/td>\n<\/tr>\n
60<\/td>\n1.6.2 Serial bus PHYs <\/td>\n<\/tr>\n
61<\/td>\n2. Normative references <\/td>\n<\/tr>\n
65<\/td>\n3. Definitions, acronyms, and abbreviations
3.1 Definitions <\/td>\n<\/tr>\n
73<\/td>\n3.2 Acronyms and abbreviations <\/td>\n<\/tr>\n
77<\/td>\n4. Short-haul copper connector and cable specification
4.1 Introduction
4.2 6-circuit Alpha connectors and cables <\/td>\n<\/tr>\n
78<\/td>\n4.2.1 6-circuit connectors
4.2.1.1 Connector plug <\/td>\n<\/tr>\n
80<\/td>\n4.2.1.2 Connector plug terminations
4.2.1.3 Connector socket <\/td>\n<\/tr>\n
83<\/td>\n4.2.1.4 Positive retention <\/td>\n<\/tr>\n
84<\/td>\n4.2.1.5 Contact finish on plug and socket contacts <\/td>\n<\/tr>\n
85<\/td>\n4.2.1.6 Termination finish on plug and contact socket terminals
4.2.1.7 Shell finish on plugs and sockets
4.2.1.8 Connector durability
4.2.2 Cables
4.2.2.1 Cable material
4.2.2.2 Cable assemblies
4.2.3 Connector and cable assembly performance criteria <\/td>\n<\/tr>\n
88<\/td>\n4.2.3.1 Performance group A: Basic mechanical dimensional conformance and electrical functionality when subjected to mechanical shock and vibration <\/td>\n<\/tr>\n
89<\/td>\n4.2.3.2 Performance group B: Low-level contact resistance when subjected to thermal shock and humidity stress <\/td>\n<\/tr>\n
90<\/td>\n4.2.3.3 Performance group C: Insulator integrity when subjected to thermal shock and humidity stress <\/td>\n<\/tr>\n
91<\/td>\n4.2.3.4 Performance group D: Contact life and durability when subjected to mechanical cycling and corrosive gas exposure <\/td>\n<\/tr>\n
93<\/td>\n4.2.3.5 Performance group E: Contact resistance and unmating force when subjected to temperature life stress <\/td>\n<\/tr>\n
94<\/td>\n4.2.3.6 Performance group F: Mechanical retention and durability <\/td>\n<\/tr>\n
95<\/td>\n4.2.3.7 Performance group G: General tests <\/td>\n<\/tr>\n
96<\/td>\n4.2.4 Signal propagation performance
4.2.4.1 Signal impedance
4.2.4.2 Signal pairs attenuation <\/td>\n<\/tr>\n
97<\/td>\n4.2.4.3 Signal pairs velocity of propagation
4.2.4.4 Signal pairs relative propagation skew
4.2.4.5 Power pair characteristic impedance
4.2.4.6 Power pair dc resistance <\/td>\n<\/tr>\n
98<\/td>\n4.2.4.7 Crosstalk
4.3 4-circuit Alpha connectors and cables
4.3.1 Connectors
4.3.1.1 Connector plug
4.3.1.2 Connector plug terminations <\/td>\n<\/tr>\n
100<\/td>\n4.3.1.3 Connector socket <\/td>\n<\/tr>\n
102<\/td>\n4.3.1.4 Contact finish on plug and socket contacts
4.3.1.5 Termination finish on plug and contact socket terminals
4.3.1.6 Shell finish on plugs and sockets
4.3.1.7 Connector durability <\/td>\n<\/tr>\n
103<\/td>\n4.3.1.8 PCB footprints <\/td>\n<\/tr>\n
104<\/td>\n4.3.2 Cables
4.3.2.1 Cable material
4.3.2.2 Cable assemblies <\/td>\n<\/tr>\n
105<\/td>\n4.3.3 Connector and cable assembly performance criteria <\/td>\n<\/tr>\n
106<\/td>\n4.3.3.1 Performance group A: Basic mechanical dimensional conformance and electrical functionality when subjected to mechanical shock and vibration <\/td>\n<\/tr>\n
107<\/td>\n4.3.3.2 Performance group B: Low-level contact resistance when subjected to thermal shock and humidity stress <\/td>\n<\/tr>\n
108<\/td>\n4.3.3.3 Performance group C: Insulator integrity when subjected to thermal shock and humidity stress <\/td>\n<\/tr>\n
109<\/td>\n4.3.3.4 Performance group D: Contact life and durability when subjected to mechanical cycling and corrosive gas exposure <\/td>\n<\/tr>\n
111<\/td>\n4.3.3.5 Performance group E: Contact resistance and unmating force when subjected to temperature life stress <\/td>\n<\/tr>\n
112<\/td>\n4.3.3.6 Performance group F: Mechanical retention and durability <\/td>\n<\/tr>\n
113<\/td>\n4.3.3.7 Performance group G: General tests <\/td>\n<\/tr>\n
115<\/td>\n4.3.4 Signal propagation performance criteria
4.3.4.1 Signal impedance
4.3.4.2 Signal pairs attenuation
4.3.4.3 Signal pairs propagation delay <\/td>\n<\/tr>\n
116<\/td>\n4.3.4.4 Signal pairs relative propagation skew
4.3.4.5 Crosstalk
4.4 9-circuit Beta and bilingual connectors and cables
4.4.1 9-circuit Beta and bilingual connectors <\/td>\n<\/tr>\n
118<\/td>\n4.4.1.1 Plug cable termination method
4.4.1.2 Socket <\/td>\n<\/tr>\n
127<\/td>\n4.4.1.3 Mating area finish on plug and socket contacts
4.4.1.4 Termination area finish on plug and socket contacts
4.4.1.5 Shell finish on plugs and sockets
4.4.1.6 Durability <\/td>\n<\/tr>\n
128<\/td>\n4.4.1.7 Socket PCB termination footprints and PHY trace routing <\/td>\n<\/tr>\n
130<\/td>\n4.4.1.8 Plug overmold
4.4.1.9 Socket orientation preference
4.4.2 Cables <\/td>\n<\/tr>\n
131<\/td>\n4.4.2.1 Reference cable material for Beta-to-Beta cable assemblies <\/td>\n<\/tr>\n
132<\/td>\n4.4.2.2 Reference cable material for bilingual-to-Alpha cable assemblies
4.4.2.3 Cable assemblies <\/td>\n<\/tr>\n
136<\/td>\n4.4.3 Connector and cable assembly performance criteria <\/td>\n<\/tr>\n
137<\/td>\n4.4.3.1 Performance group A: Basic mechanical dimensional conformance and electrical functionality when subjected to mechanical shock and vibration <\/td>\n<\/tr>\n
138<\/td>\n4.4.3.2 Performance group B: Low-level contact resistance when subjected to thermal shock and humidity stress <\/td>\n<\/tr>\n
139<\/td>\n4.4.3.3 Performance group C: Insulator integrity when subjected to thermal shock and humidity stress <\/td>\n<\/tr>\n
140<\/td>\n4.4.3.4 Performance group D: Contact life and durability when subjected to mechanical cycling and corrosive gas exposure <\/td>\n<\/tr>\n
142<\/td>\n4.4.3.5 Performance group E: Contact resistance and unmating force when subjected to temperature life stress <\/td>\n<\/tr>\n
143<\/td>\n4.4.3.6 Performance group F: Mechanical retention and durability
4.4.3.7 Performance group G: General tests <\/td>\n<\/tr>\n
145<\/td>\n4.4.4 Signal propagation performance criteria
4.4.4.1 Test hardware
4.4.4.1.1 Connector-only differential test fixture <\/td>\n<\/tr>\n
146<\/td>\n4.4.4.1.2 Cable assembly differential test fixture <\/td>\n<\/tr>\n
147<\/td>\n4.4.4.1.3 Test fixture schematic <\/td>\n<\/tr>\n
148<\/td>\n4.4.4.1.4 Pad position to PHY function map
4.4.4.2 Signal impedance <\/td>\n<\/tr>\n
149<\/td>\n4.4.4.3 Signal pairs attenuation <\/td>\n<\/tr>\n
150<\/td>\n4.4.4.4 Signal pairs velocity of propagation <\/td>\n<\/tr>\n
151<\/td>\n4.4.4.5 Signal pairs intrapair propagation skew <\/td>\n<\/tr>\n
152<\/td>\n4.4.4.6 Crosstalk
4.4.4.6.1 Connector
4.4.4.6.2 Cable assembly
4.4.4.7 Power <\/td>\n<\/tr>\n
153<\/td>\n5. Backplane PHY specification
5.1 Backplane PHY services <\/td>\n<\/tr>\n
154<\/td>\n5.1.1 Backplane PHY bus management services for the management layer
5.1.1.1 PHY control request (PH_CONTROL.request)
5.1.1.2 PHY control confirmation (PH_CONTROL.confirmation) <\/td>\n<\/tr>\n
155<\/td>\n5.1.1.3 PHY event indication (PH_EVENT.indication)
5.1.2 PHY layer arbitration services for the link layer
5.1.2.1 PHY arbitration request (PH_ARB.request) <\/td>\n<\/tr>\n
156<\/td>\n5.1.2.2 PHY arbitration confirmation (PH_ARB.confirmation)
5.1.3 PHY layer data services for the link layer
5.1.3.1 PHY clock indication (PH_CLOCK.indication)
5.1.3.2 PHY data request (PH_DATA.request) <\/td>\n<\/tr>\n
157<\/td>\n5.1.3.3 PHY data indication (PH_DATA.indication)
5.2 Backplane physical connection specification <\/td>\n<\/tr>\n
158<\/td>\n5.2.1 Media attachment
5.2.1.1 Distribution of nodes
5.2.1.2 Fault detection and isolation <\/td>\n<\/tr>\n
159<\/td>\n5.2.1.3 Live insertion
5.2.2 Media signal interface
5.2.2.1 Definition of logic states <\/td>\n<\/tr>\n
160<\/td>\n5.2.2.2 Bit rates
5.2.2.3 Transition times
5.2.2.4 Noise rejection
5.2.3 Media signal timing
5.2.3.1 Backplane transmit data timing <\/td>\n<\/tr>\n
161<\/td>\n5.2.3.2 Backplane receive data timing <\/td>\n<\/tr>\n
162<\/td>\n5.2.3.3 Backplane and transceiver skew
5.2.4 Backplane PHY timing <\/td>\n<\/tr>\n
163<\/td>\n5.2.4.1 Arbitration clock rate
5.2.4.2 Bus synchronization and propagation delay <\/td>\n<\/tr>\n
164<\/td>\n5.2.4.3 Arbitration bit timing <\/td>\n<\/tr>\n
166<\/td>\n5.3 Backplane PHY facilities
5.3.1 Coding
5.3.2 Backplane PHY signals <\/td>\n<\/tr>\n
167<\/td>\n5.3.3 Gap timing <\/td>\n<\/tr>\n
168<\/td>\n5.3.4 Arbitration sequence
5.3.4.1 Arbitration number
5.3.4.2 Priority <\/td>\n<\/tr>\n
169<\/td>\n5.3.4.3 Format of arbitration sequence
5.4 Backplane PHY operation <\/td>\n<\/tr>\n
170<\/td>\n5.4.1 Arbitration
5.4.1.1 Fairness intervals <\/td>\n<\/tr>\n
171<\/td>\n5.4.1.2 Fair arbitration <\/td>\n<\/tr>\n
172<\/td>\n5.4.1.3 Urgent arbitration <\/td>\n<\/tr>\n
173<\/td>\n5.4.1.4 Arbitration by the cycle master
5.4.1.5 Isochronous arbitration
5.4.1.6 Immediate arbitration
5.4.2 Backplane environment packet transmission and reception <\/td>\n<\/tr>\n
174<\/td>\n5.4.2.1 Backplane environment packet transmission <\/td>\n<\/tr>\n
175<\/td>\n5.4.2.2 Backplane environment packet reception <\/td>\n<\/tr>\n
176<\/td>\n5.5 Backplane initialization and reset
5.5.1 Backplane PHY reset
5.5.1.1 Command reset
5.5.1.2 Bus reset
5.5.2 Backplane PHY initialization <\/td>\n<\/tr>\n
177<\/td>\n6. Link layer specification
6.1 Link layer services <\/td>\n<\/tr>\n
178<\/td>\n6.1.1 Link layer bus management services for the node controller
6.1.1.1 Link control request (LK_CONTROL.request) <\/td>\n<\/tr>\n
179<\/td>\n6.1.1.2 Link control confirmation (LK_CONTROL.confirmation)
6.1.1.3 Link event indication (LK_EVENT.indication)
6.1.1.4 Link remote configuration request (LK_CONFIG.request) (cable environment only) <\/td>\n<\/tr>\n
180<\/td>\n6.1.1.5 Link remote configuration indication (LK_CONFIG.indication) (cable environment only)
6.1.2 Link layer asynchronous data services for the transaction layer
6.1.2.1 Link data request (LK_DATA.request) <\/td>\n<\/tr>\n
181<\/td>\n6.1.2.2 Link data confirmation (LK_DATA.confirmation)
6.1.2.3 Link data indication (LK_DATA.indication) <\/td>\n<\/tr>\n
182<\/td>\n6.1.2.4 Link data response (LK_DATA.response)
6.1.2.5 Link bus indication (LK_BUS.indication)
6.1.3 Link layer isochronous data services for application layers
6.1.3.1 Link isochronous control request (LK_ISO_CONTROL.request) <\/td>\n<\/tr>\n
183<\/td>\n6.1.3.2 Link cycle sync indication (LK_CYCLE.indication)
6.1.3.3 Link isochronous request (LK_ISO.request)
6.1.3.4 Link isochronous indication (LK_ISO.indication) <\/td>\n<\/tr>\n
184<\/td>\n6.2 Link layer facilities
6.2.1 Primary packets <\/td>\n<\/tr>\n
185<\/td>\n6.2.2 Asynchronous packets <\/td>\n<\/tr>\n
186<\/td>\n6.2.2.1 Asynchronous packets with no-data payload <\/td>\n<\/tr>\n
187<\/td>\n6.2.2.1.1 Read request for data quadlet
6.2.2.1.2 Write response
6.2.2.2 Asynchronous packet formats with data quadlet payload <\/td>\n<\/tr>\n
188<\/td>\n6.2.2.2.1 Read request for data block
6.2.2.2.2 Write request for data quadlet
6.2.2.2.3 Cycle start <\/td>\n<\/tr>\n
189<\/td>\n6.2.2.2.4 Read response for data quadlet <\/td>\n<\/tr>\n
190<\/td>\n6.2.2.3 Asynchronous packet formats with data block payload
6.2.2.3.1 Write request for data block <\/td>\n<\/tr>\n
191<\/td>\n6.2.2.3.2 Lock request <\/td>\n<\/tr>\n
192<\/td>\n6.2.2.3.3 Read response for data block <\/td>\n<\/tr>\n
193<\/td>\n6.2.2.3.4 Lock response
6.2.3 Isochronous packets
6.2.3.1 Isochronous packet components <\/td>\n<\/tr>\n
194<\/td>\n6.2.3.2 Isochronous data block packet format <\/td>\n<\/tr>\n
195<\/td>\n6.2.4 Asynchronous streams
6.2.4.1 Asynchronous stream packet format <\/td>\n<\/tr>\n
196<\/td>\n6.2.4.2 Global asynchronous stream packet (GASP) format <\/td>\n<\/tr>\n
197<\/td>\n6.2.4.3 Loose vs. strict isochronous packet reception
6.2.5 Primary packet components
6.2.5.1 Reserved fields, codes, and values
6.2.5.2 Destination address
6.2.5.2.1 Destination ID (destination_lD)
6.2.5.2.2 Destination offset (destination_offset) <\/td>\n<\/tr>\n
198<\/td>\n6.2.5.3 Transaction label (tl)
6.2.5.4 Retry code (rt)
6.2.5.5 Transaction code (tcode) <\/td>\n<\/tr>\n
200<\/td>\n6.2.5.6 Priority (pri)
6.2.5.7 Source ID (source_ID)
6.2.5.8 Data length (data_length)
6.2.5.9 Extended transaction code (extended_tcode) <\/td>\n<\/tr>\n
201<\/td>\n6.2.5.10 Response code (rcode)
6.2.5.11 Data field
6.2.5.12 Tag (isochronous stream packets)
6.2.5.13 Channel <\/td>\n<\/tr>\n
202<\/td>\n6.2.5.14 Synchronization code (sy)
6.2.5.15 CRCs
6.2.5.15.1 Definitions <\/td>\n<\/tr>\n
203<\/td>\n6.2.5.15.2 CRC generation equations
6.2.5.15.3 CRC checking
6.2.6 Acknowledge packets <\/td>\n<\/tr>\n
204<\/td>\n6.2.6.1 Acknowledge packet format
6.2.6.2 ACK packet components
6.2.6.2.1 Reserved acknowledge codes
6.2.6.2.2 Acknowledge code (ack_code) <\/td>\n<\/tr>\n
206<\/td>\n6.2.6.2.3 Acknowledge parity (ack_parity)
6.3 Link layer operation
6.3.1 Overview of link layer operation
6.3.1.1 Communication with the PHY layer <\/td>\n<\/tr>\n
207<\/td>\n6.3.1.2 Priority arbitration for PHY packets and response packets
6.3.1.3 Sending an asynchronous packet
6.3.1.4 Receiving an asynchronous packet <\/td>\n<\/tr>\n
208<\/td>\n6.3.1.5 Sending an acknowledge concatenated to an asynchronous packet
6.3.1.6 Isochronous cycles
6.3.1.7 Sending isochronous packets
6.3.1.8 Receiving an isochronous packet <\/td>\n<\/tr>\n
209<\/td>\n6.3.2 Cycle sync event <\/td>\n<\/tr>\n
210<\/td>\n6.3.3 Details of link layer operation <\/td>\n<\/tr>\n
211<\/td>\n6.3.3.1 Link initialization
6.3.3.2 Asynchronous operation <\/td>\n<\/tr>\n
214<\/td>\n6.3.3.3 Isochronous operation <\/td>\n<\/tr>\n
216<\/td>\n6.4 Link layer reference code <\/td>\n<\/tr>\n
219<\/td>\n7. Transaction layer specification
7.1 Transaction layer services
7.1.1 Transaction layer bus management services for SBM <\/td>\n<\/tr>\n
220<\/td>\n7.1.1.1 Transaction control request (TR_CONTROL.request)
7.1.1.2 Transaction control confirmation (TR_CONTROL.confirmation)
7.1.1.3 Transaction event indication (TR_EVENT.indication)
7.1.2 Transaction layer data services for applications and bus management <\/td>\n<\/tr>\n
221<\/td>\n7.1.2.1 Transaction data request (TR_DATA.request)
7.1.2.2 Transaction data confirmation (TR_DATA.confirmation) <\/td>\n<\/tr>\n
222<\/td>\n7.1.2.3 Transaction data indication (TR_DATA.indication)
7.1.2.4 Transaction data response (TR_DATA.response) <\/td>\n<\/tr>\n
223<\/td>\n7.2 Transaction facilities
7.2.1 Split transaction timer
7.2.2 Transaction retry limit
7.3 Transaction operation
7.3.1 Overview of transaction layer operations <\/td>\n<\/tr>\n
224<\/td>\n7.3.1.1 Read transactions
7.3.1.2 Write transactions <\/td>\n<\/tr>\n
225<\/td>\n7.3.1.3 Lock transactions
7.3.1.4 Response codes (rcode)
7.3.1.4.1 No response
7.3.1.4.2 resp_complete <\/td>\n<\/tr>\n
226<\/td>\n7.3.1.4.3 resp_conflict_error
7.3.1.4.4 resp_data_error
7.3.1.4.5 resp_type_error <\/td>\n<\/tr>\n
227<\/td>\n7.3.1.4.6 resp_address_error
7.3.1.5 Error handling
7.3.2 Transaction completion definitions <\/td>\n<\/tr>\n
228<\/td>\n7.3.2.1 Unified transaction
7.3.2.2 Split transaction
7.3.2.3 Concatenated transaction
7.3.2.4 Broadcast transaction
7.3.2.5 Pending transaction
7.3.3 Details of transaction layer operation <\/td>\n<\/tr>\n
229<\/td>\n7.3.3.1 Outbound transaction state machine
7.3.3.1.1 Outbound transaction state machine initialization <\/td>\n<\/tr>\n
230<\/td>\n7.3.3.1.2 Sending a transaction request <\/td>\n<\/tr>\n
231<\/td>\n7.3.3.1.3 Sending a transaction response <\/td>\n<\/tr>\n
232<\/td>\n7.3.3.2 Inbound transaction state machine
7.3.3.2.1 Inbound transaction state machine initialization <\/td>\n<\/tr>\n
233<\/td>\n7.3.3.2.2 Responding to a transaction request <\/td>\n<\/tr>\n
235<\/td>\n7.3.3.2.3 Responding to a transaction response <\/td>\n<\/tr>\n
236<\/td>\n7.3.4 Transaction types
7.3.4.1 Read transactions
7.3.4.2 Write transactions
7.3.4.3 Lock transactions <\/td>\n<\/tr>\n
237<\/td>\n7.3.5 Retry protocols <\/td>\n<\/tr>\n
238<\/td>\n7.3.5.1 Outbound subaction retry protocol <\/td>\n<\/tr>\n
239<\/td>\n7.3.5.2 Inbound subaction single-phase retry protocol
7.3.5.3 Inbound subaction dual-phase retry protocol <\/td>\n<\/tr>\n
242<\/td>\n7.4 CSR architecture transactions mapped to serial bus <\/td>\n<\/tr>\n
245<\/td>\n8. Serial bus management (SBM) specification
8.1 SBM summary
8.1.1 Node control
8.1.2 IRM (cable environment)
8.1.3 IRM (backplane environment)
8.1.4 Bus manager (cable environment) <\/td>\n<\/tr>\n
246<\/td>\n8.2 SBM services
8.2.1 Serial bus control request (SB_CONTROL.request) <\/td>\n<\/tr>\n
247<\/td>\n8.2.2 Serial bus control confirmation (SB_CONTROL.confirmation)
8.2.3 Serial bus event indication (SB_EVENT. indication) <\/td>\n<\/tr>\n
249<\/td>\n8.3 SBM facilities
8.3.1 Node capabilities taxonomy
8.3.1.1 Repeater (cable environment)
8.3.1.2 Transaction capable <\/td>\n<\/tr>\n
250<\/td>\n8.3.1.3 Isochronous capable
8.3.1.4 Cycle master capable
8.3.1.5 IRM capable
8.3.1.6 Bus manager capable (cable environment) <\/td>\n<\/tr>\n
251<\/td>\n8.3.2 Command and status registers
8.3.2.1 Reset conditions <\/td>\n<\/tr>\n
252<\/td>\n8.3.2.2 CSR architecture core registers
8.3.2.2.1 STATE_CLEAR register <\/td>\n<\/tr>\n
254<\/td>\n8.3.2.2.2 STATE_SET register
8.3.2.2.3 NODE_IDS register <\/td>\n<\/tr>\n
255<\/td>\n8.3.2.2.4 Command reset effects
8.3.2.2.5 INDIRECT_ADDRESS and INDIRECT_DATA registers
8.3.2.2.6 SPLIT_TIMEOUT register <\/td>\n<\/tr>\n
256<\/td>\n8.3.2.2.7 ARGUMENT, TEST_START, and TEST_STATUS registers <\/td>\n<\/tr>\n
257<\/td>\n8.3.2.2.8 UNITS_BASE, UNITS_BOUND, MEMORY_BASE, and MEMORY_BOUND registers
8.3.2.2.9 INTERRUPT_TARGET and INTERRUPT_MASK registers
8.3.2.2.10 CLOCK_VALUE, CLOCK_TICK_PERIOD, CLOCK_STROBE_ARRIVED, and CLOCK_INFO registers
8.3.2.2.11 MESSAGE_REQUEST and MESSAGE_RESPONSE registers
8.3.2.3 Serial-Bus-dependent registers <\/td>\n<\/tr>\n
258<\/td>\n8.3.2.3.1 CYCLE_TIME register <\/td>\n<\/tr>\n
259<\/td>\n8.3.2.3.2 BUS_TIME register <\/td>\n<\/tr>\n
260<\/td>\n8.3.2.3.3 POWER_FAIL_IMMINENT register
8.3.2.3.4 POWER_SOURCE register <\/td>\n<\/tr>\n
261<\/td>\n8.3.2.3.5 BUSY_TIMEOUT register <\/td>\n<\/tr>\n
262<\/td>\n8.3.2.3.6 PRIORITY_BUDGET register <\/td>\n<\/tr>\n
263<\/td>\n8.3.2.3.7 BUS_MANAGER_ID register <\/td>\n<\/tr>\n
264<\/td>\n8.3.2.3.8 BANDWIDTH_AVAILABLE register <\/td>\n<\/tr>\n
266<\/td>\n8.3.2.3.9 CHANNELS_AVAILABLE register <\/td>\n<\/tr>\n
267<\/td>\n8.3.2.3.10 MAINT_CONTROL register <\/td>\n<\/tr>\n
268<\/td>\n8.3.2.3.11 MAINT_UTILITY register <\/td>\n<\/tr>\n
269<\/td>\n8.3.2.3.12 BROADCAST_CHANNEL register
8.3.2.4 Unit registers <\/td>\n<\/tr>\n
270<\/td>\n8.3.2.5 TOPOLOGY_MAP registers (cable environment) <\/td>\n<\/tr>\n
271<\/td>\n8.3.2.6 Configuration ROM <\/td>\n<\/tr>\n
272<\/td>\n8.3.2.6.1 Organizationally Unique Identifier (OUI)
8.3.2.6.2 Minimal ROM format
8.3.2.6.3 General ROM format <\/td>\n<\/tr>\n
273<\/td>\n8.3.2.6.4 Configuration ROM Bus_Info_Block <\/td>\n<\/tr>\n
275<\/td>\n8.3.2.6.5 Root_Directory <\/td>\n<\/tr>\n
276<\/td>\n8.3.2.6.6 Unit_Directories <\/td>\n<\/tr>\n
277<\/td>\n8.3.3 SBM variables
8.4 SBM operations
8.4.1 Bus configuration procedures (backplane environment) <\/td>\n<\/tr>\n
278<\/td>\n8.4.1.1 Unmanaged bus (backplane environment)
8.4.1.2 Determination of the IRM (backplane environment)
8.4.1.3 Determination of the cycle master (backplane environment)
8.4.2 Bus configuration procedures (cable environment)
8.4.2.1 Unmanaged bus (cable environment) <\/td>\n<\/tr>\n
279<\/td>\n8.4.2.2 Prior isochronous traffic (cable environment)
8.4.2.3 Determination of the IRM (cable environment) <\/td>\n<\/tr>\n
280<\/td>\n8.4.2.4 Reallocation of prior isochronous resources (cable environment)
8.4.2.5 Determination of the bus manager (cable environment)
8.4.2.6 Determination of the cycle master (cable environment) <\/td>\n<\/tr>\n
281<\/td>\n8.4.2.7 Determination of the root (cable environment) <\/td>\n<\/tr>\n
282<\/td>\n8.4.2.8 Power management by the IRM (cable environment)
8.4.2.9 Allocation of new isochronous resources (cable environment)
8.4.3 Isochronous resource allocation (cable environment)
8.4.3.1 Bandwidth allocation <\/td>\n<\/tr>\n
283<\/td>\n8.4.3.2 Channel allocation <\/td>\n<\/tr>\n
284<\/td>\n8.4.3.3 Bandwidth set-aside
8.4.3.4 Isochronous requests with no cycle master
8.4.4 Power management (cable environment) <\/td>\n<\/tr>\n
285<\/td>\n8.4.4.1 PHY power management
8.4.4.2 Link power management
8.4.4.3 Unit power management
8.4.4.4 Power management by the bus manager <\/td>\n<\/tr>\n
286<\/td>\n8.4.4.5 Power management by the IRM
8.4.5 Topology management (cable environment)
8.4.5.1 Accessing the topology map <\/td>\n<\/tr>\n
287<\/td>\n8.4.5.2 Gap count optimization
8.4.6 Filtered packets on an asynchronous-only B_bus
8.5 Bus configuration state machines (cable environment) <\/td>\n<\/tr>\n
288<\/td>\n8.5.1 Candidate cycle master states <\/td>\n<\/tr>\n
289<\/td>\n8.5.2 Candidate IRM states <\/td>\n<\/tr>\n
290<\/td>\n8.5.3 Candidate bus manager states <\/td>\n<\/tr>\n
292<\/td>\n8.5.4 Abdication by the bus manager <\/td>\n<\/tr>\n
293<\/td>\n9. Short-haul copper PMD electrical specification
9.1 Introduction
9.1.1 Short-haul copper PHY operation <\/td>\n<\/tr>\n
295<\/td>\n9.1.2 Short-haul copper physical connection specification <\/td>\n<\/tr>\n
296<\/td>\n9.1.3 Interfaces
9.1.4 Modes of operation
9.2 Data-strobe (DS) mode specification
9.2.1 Port interface <\/td>\n<\/tr>\n
298<\/td>\n9.2.1.1 Signal amplitude <\/td>\n<\/tr>\n
299<\/td>\n9.2.1.2 Common mode voltage <\/td>\n<\/tr>\n
300<\/td>\n9.2.1.3 Speed signaling <\/td>\n<\/tr>\n
301<\/td>\n9.2.1.4 Arbitration signal voltages <\/td>\n<\/tr>\n
302<\/td>\n9.2.1.5 Input impedance
9.2.1.6 Noise <\/td>\n<\/tr>\n
303<\/td>\n9.2.1.7 Driver and receiver fault protection
9.2.2 Media signal timing
9.2.2.1 Data rate
9.2.2.2 Data signal rise and fall times <\/td>\n<\/tr>\n
304<\/td>\n9.2.2.3 Jitter and skew
9.2.3 Coding
9.2.4 DS PHY signals <\/td>\n<\/tr>\n
305<\/td>\n9.2.5 DS PHY line states <\/td>\n<\/tr>\n
307<\/td>\n9.2.6 Cable PHY timing constants <\/td>\n<\/tr>\n
312<\/td>\n9.2.7 Gap timing <\/td>\n<\/tr>\n
313<\/td>\n9.2.8 Speed signal sampling and filtering <\/td>\n<\/tr>\n
314<\/td>\n9.2.9 Data transmission and reception
9.2.9.1 Data transmission <\/td>\n<\/tr>\n
315<\/td>\n9.2.9.2 Data reception and repeat
9.3 Beta mode specification
9.3.1 Transmitter electrical specifications <\/td>\n<\/tr>\n
319<\/td>\n9.3.2 Receiver electrical specifications <\/td>\n<\/tr>\n
323<\/td>\n9.3.2.1 S3200 equalization
9.3.3 Electrical measurements
9.3.3.1 Transmit rise and fall time
9.3.3.2 Transmit skew <\/td>\n<\/tr>\n
324<\/td>\n9.3.3.3 Transmit eye (normalized and absolute)
9.3.3.4 Rise and fall time setting for receiver jitter tolerance test
9.3.3.5 Skew setting for receiver jitter tolerance test <\/td>\n<\/tr>\n
325<\/td>\n9.3.3.6 Receiver jitter tolerance
9.3.3.7 Minimum amplitude for receiver jitter tolerance test <\/td>\n<\/tr>\n
326<\/td>\n9.3.3.8 S3200 BER
9.3.3.9 S3200 electrical test configuration
9.3.4 DC biasing <\/td>\n<\/tr>\n
327<\/td>\n9.3.5 Toning and signal detect
9.3.5.1 Connection tone <\/td>\n<\/tr>\n
328<\/td>\n9.3.5.2 PMD signal detect function <\/td>\n<\/tr>\n
329<\/td>\n9.3.5.3 Application note
9.3.6 Jitter specifications <\/td>\n<\/tr>\n
333<\/td>\n9.3.7 Intrapair skew
9.3.8 Termination and isolation
9.3.8.1 Bilingual port termination and isolation <\/td>\n<\/tr>\n
334<\/td>\n9.3.8.2 Beta-only port termination and isolation <\/td>\n<\/tr>\n
335<\/td>\n9.3.8.3 PIL-FOP termination and isolation <\/td>\n<\/tr>\n
336<\/td>\n9.4 Cable power and ground
9.4.1 Node power classes <\/td>\n<\/tr>\n
338<\/td>\n9.4.2 Ground isolation <\/td>\n<\/tr>\n
339<\/td>\n9.4.2.1 Primary power providers
9.4.2.2 Secondary power provider
9.4.3 Protection against late VG <\/td>\n<\/tr>\n
343<\/td>\n10. Glass optical fiber (GOF) PMD specification <\/td>\n<\/tr>\n
344<\/td>\n10.1 PMD block diagram
10.2 PMD-to-MDI optical specifications <\/td>\n<\/tr>\n
345<\/td>\n10.3 Transmitter optical specifications
10.4 Receiver optical specifications <\/td>\n<\/tr>\n
346<\/td>\n10.5 Worst-case connection optical power budget and penalties <\/td>\n<\/tr>\n
347<\/td>\n10.6 Optical jitter specifications <\/td>\n<\/tr>\n
349<\/td>\n10.7 Optical measurement requirements
10.7.1 Center wavelength and spectral width measurements
10.7.2 Optical power measurements
10.7.3 Extinction ratio measurements
10.7.4 Relative intensity noise (RIN)
10.7.5 Transmitter optical waveform (transmit eye) <\/td>\n<\/tr>\n
350<\/td>\n10.7.6 Transmit rise and fall characteristics <\/td>\n<\/tr>\n
351<\/td>\n10.7.7 Receiver sensitivity measurements
10.7.8 Jitter measurements
10.8 CPR measurement
10.9 Optical connection cabling model
10.9.1 Characteristics of the fiber optic medium <\/td>\n<\/tr>\n
352<\/td>\n10.9.2 Optical fiber and cable
10.9.3 Multimode connector insertion loss
10.9.4 Optical connection return loss
10.10 Optical connection <\/td>\n<\/tr>\n
353<\/td>\n10.11 Fiber launch conditions: OFL <\/td>\n<\/tr>\n
355<\/td>\n11. PMD specification of fiber media with PN connector
11.1 Scope <\/td>\n<\/tr>\n
356<\/td>\n11.2 PMD block diagram
11.3 Cables <\/td>\n<\/tr>\n
357<\/td>\n11.4 Connector <\/td>\n<\/tr>\n
358<\/td>\n11.5 Connector and cable assembly performance criteria
11.6 Optical fiber interface
11.7 Optical jitter specifications
11.8 Permitted number of segments <\/td>\n<\/tr>\n
363<\/td>\n12. Unshielded twisted pair (UTP) PMD specification <\/td>\n<\/tr>\n
364<\/td>\n12.1 Overview
12.2 PMD block diagram
12.3 Operation of UTP connections <\/td>\n<\/tr>\n
365<\/td>\n12.4 Media specification
12.4.1 100 Ohm UTP connection segment specification
12.4.2 100 Ohm UTP cable specification
12.4.3 Connecting hardware <\/td>\n<\/tr>\n
366<\/td>\n12.4.4 Media interface connector <\/td>\n<\/tr>\n
367<\/td>\n12.4.5 Autocrossover
12.5 PMD electrical specifications
12.5.1 Galvanic isolation <\/td>\n<\/tr>\n
368<\/td>\n12.5.2 Transmitter specifications <\/td>\n<\/tr>\n
371<\/td>\n12.5.3 Receiver specifications
12.5.3.1 Receiver input signals
12.5.3.2 PMD signal detect function <\/td>\n<\/tr>\n
373<\/td>\n12.6 PMD implementation <\/td>\n<\/tr>\n
375<\/td>\n13. Beta mode port specification
13.1 Overview <\/td>\n<\/tr>\n
376<\/td>\n13.2 Port functions
13.2.1 Overview <\/td>\n<\/tr>\n
377<\/td>\n13.2.2 Naming conventions
13.2.3 Control mapping <\/td>\n<\/tr>\n
378<\/td>\n13.2.4 Request types
13.2.4.1 BOSS arbitration request mapping <\/td>\n<\/tr>\n
380<\/td>\n13.2.4.2 Configuration requests
13.2.5 Scrambling <\/td>\n<\/tr>\n
381<\/td>\n13.2.5.1 Data scrambling <\/td>\n<\/tr>\n
382<\/td>\n13.2.5.2 Request symbol scrambling <\/td>\n<\/tr>\n
383<\/td>\n13.2.5.3 Control symbol scrambling <\/td>\n<\/tr>\n
384<\/td>\n13.2.6 Coding
13.2.6.1 8B\/10B character coding for data and request types <\/td>\n<\/tr>\n
385<\/td>\n13.2.6.1.1 8B\/10B run length and dc balance
13.2.6.1.2 8B\/10B code construction
13.2.6.1.3 8B\/10B valid data characters <\/td>\n<\/tr>\n
394<\/td>\n13.2.6.1.4 8B\/10B valid special characters
13.2.6.2 Control coding <\/td>\n<\/tr>\n
395<\/td>\n13.2.6.2.1 Valid control code characters
13.2.6.2.2 Control code run length and dc balance <\/td>\n<\/tr>\n
396<\/td>\n13.2.6.2.3 Control code error detection
13.2.7 Character transmission
13.2.8 Decoding
13.2.8.1 Bit and character synchronization
13.2.8.2 Data and control character decoding and error detection
13.2.8.3 Special character decoding
13.2.9 Receiver running disparity <\/td>\n<\/tr>\n
397<\/td>\n13.2.10 Descrambling
13.3 Beta mode port operation
13.3.1 Transmit operations
13.3.1.1 Control transmission <\/td>\n<\/tr>\n
398<\/td>\n13.3.1.2 Request transmission
13.3.1.3 Packet transmission <\/td>\n<\/tr>\n
399<\/td>\n13.3.1.4 Speed signaling <\/td>\n<\/tr>\n
400<\/td>\n13.3.1.5 Payload transmission <\/td>\n<\/tr>\n
401<\/td>\n13.3.2 Receive operations
13.3.2.1 Port training
13.3.2.1.1 Loss of synchronization detection procedure
13.3.2.1.2 Resynchronization procedure <\/td>\n<\/tr>\n
402<\/td>\n13.3.2.2 Control reception
13.3.2.3 Request type reception <\/td>\n<\/tr>\n
403<\/td>\n13.3.2.4 DATA_PREFIX reception
13.3.2.5 Speed code determination <\/td>\n<\/tr>\n
404<\/td>\n13.3.2.6 Payload reception <\/td>\n<\/tr>\n
405<\/td>\n13.3.2.7 Error reporting
13.4 Beta port state machines <\/td>\n<\/tr>\n
406<\/td>\n13.4.1 Port transmit state machine <\/td>\n<\/tr>\n
407<\/td>\n13.4.2 Port receive state machine <\/td>\n<\/tr>\n
409<\/td>\n14. Connection management
14.1 Overview <\/td>\n<\/tr>\n
410<\/td>\n14.2 Port characteristics
14.2.1 Requirements <\/td>\n<\/tr>\n
411<\/td>\n14.2.2 Properties
14.3 Functions, variables, and constants <\/td>\n<\/tr>\n
414<\/td>\n14.4 Node-level port controller
14.5 Port connection manager state machine <\/td>\n<\/tr>\n
419<\/td>\n14.6 Standby <\/td>\n<\/tr>\n
420<\/td>\n14.6.1 Nephew node characteristics
14.6.2 Uncle node characteristics <\/td>\n<\/tr>\n
421<\/td>\n14.7 Loop prevention
14.7.1 Test port <\/td>\n<\/tr>\n
422<\/td>\n14.7.2 Loop test data (LTD)
14.7.2.1 M bit
14.7.2.2 G bit <\/td>\n<\/tr>\n
423<\/td>\n14.7.2.3 test_value number
14.7.3 Holding register (HR)
14.7.4 Maximum occupancy timer
14.7.5 Loop test symbol (LTS) <\/td>\n<\/tr>\n
424<\/td>\n14.7.6 Loop test packet (LTP)
14.7.7 Test port selection
14.7.8 Loop test <\/td>\n<\/tr>\n
425<\/td>\n14.7.9 Completing the attach <\/td>\n<\/tr>\n
426<\/td>\n14.7.10 Received ATTACH_REQUEST or bus reset
14.7.11 Loop Disabled state
14.7.12 Connections to Alpha nodes
14.7.13 Loop detection during bus initialization <\/td>\n<\/tr>\n
427<\/td>\n14.7.14 Minimal LTP support
14.7.15 Isolated node behavior
14.8 Connection management
14.8.1 Connection detection
14.8.2 Connection detection and mode determination algorithm <\/td>\n<\/tr>\n
428<\/td>\n14.8.3 Beta-mode speed negotiation <\/td>\n<\/tr>\n
430<\/td>\n14.8.4 Disabled ports <\/td>\n<\/tr>\n
431<\/td>\n14.9 T-mode connectivity and operation
14.10 Simultaneous support for Beta mode and T-mode
14.11 Negotiation
14.11.1 Overview <\/td>\n<\/tr>\n
432<\/td>\n14.11.2 S100 Beta mode parallel negotiation
14.11.2.1 Clause 22 in IEEE Std 802.3-2005
14.11.3 Differences between T-mode and IEEE 802.3 negotiation <\/td>\n<\/tr>\n
433<\/td>\n14.11.3.1 Clause 28 in IEEE Std 802.3-2005
14.11.3.1.1 IEEE 802.3 (Clause 28) interface to MDI
14.11.3.1.2 IEEE 802.3 (28.3) Auto-Negotiation arbitration state machine(s)
14.11.3.1.3 Subclause 28.3.1 in IEEE Std 802.3-2005 <\/td>\n<\/tr>\n
434<\/td>\n14.11.3.1.4 Figure 28-16 in IEEE Std 802.3-2005 <\/td>\n<\/tr>\n
435<\/td>\n14.11.3.2 Annex 28A in IEEE Std 802.3-2005
14.11.3.3 Annex 28B in IEEE Std 802.3-2005
14.11.3.4 Annex 28C in IEEE Std 802.3-2005
14.11.3.4.1 IEEE 802.3 (28C.6) Message Code 5 ( OUI tag code) <\/td>\n<\/tr>\n
436<\/td>\n14.11.3.4.2 IEEE 802.3 (28C.10) Message Code 8 (1000BASE-T technology message code)
14.11.3.5 Subclause 40.5 in IEEE Std 802.3-2005
14.11.3.5.1 Subclause 40.5.1.1 in IEEE Std 802.3-2005
14.11.3.5.2 IEEE 802.3 (40.5.1.2) next page usage <\/td>\n<\/tr>\n
437<\/td>\n15. PHY register map
15.1 Arbitration compliance levels
15.1.1 Arbitration Compliance Level A
15.1.2 Arbitration Compliance Level B
15.2 PHY register map for the cable environment <\/td>\n<\/tr>\n
442<\/td>\n15.2.1 Port Status page <\/td>\n<\/tr>\n
446<\/td>\n15.2.2 Vendor Identification page <\/td>\n<\/tr>\n
447<\/td>\n15.3 PHY register map for the backplane environment <\/td>\n<\/tr>\n
448<\/td>\n15.4 Integrated link and PHY <\/td>\n<\/tr>\n
449<\/td>\n16. Data routing, arbitration, and control
16.1 Overview <\/td>\n<\/tr>\n
450<\/td>\n16.2 PHY services <\/td>\n<\/tr>\n
451<\/td>\n16.2.1 Cable PHY bus management services for the management layer
16.2.1.1 PHY control request (PH_CONTROL.request)
16.2.1.2 PHY control confirmation (PH_CONTROL.confirmation)
16.2.1.3 PHY event indication (PH_EVENT.indication) <\/td>\n<\/tr>\n
452<\/td>\n16.2.1.4 PHY event response (PH_EVENT.response)
16.2.1.5 PHY link type inquiry indication (PH_LINK_TYPE.indication) and response (PH_LINK_TYPE.response) <\/td>\n<\/tr>\n
453<\/td>\n16.2.2 PHY arbitration services for the link layer
16.2.2.1 PHY arbitration request (PH_ARB.request) <\/td>\n<\/tr>\n
455<\/td>\n16.2.2.2 PHY arbitration confirmation (PH_ARB.conf)
16.2.3 PHY data services for the link layer <\/td>\n<\/tr>\n
456<\/td>\n16.2.3.1 PHY clock indication (PH_CLOCK.indication)
16.2.3.2 PHY data request (PH_DATA.request) <\/td>\n<\/tr>\n
457<\/td>\n16.2.3.3 PHY data indication (PH_DATA.indication)
16.2.4 PHY-link interface block <\/td>\n<\/tr>\n
458<\/td>\n16.2.5 PMD services for the PHY
16.2.5.1 PMD control request (PMD_CONTROL.request)
16.2.5.2 PMD status request (PMD_STATUS.request) and confirmation (PMD_STATUS.confirmation) <\/td>\n<\/tr>\n
459<\/td>\n16.2.5.3 PMD Beta port data indication (PMD_DATA.indication)
16.2.5.4 PMD Beta port transmit data request (PMD_DATA.request)
16.2.5.5 PMD DS port receive signal request (PMD_DSPORT_SIGNAL.request) and confirmation (PMD_DSPORT_SIGNAL.confirmation) <\/td>\n<\/tr>\n
460<\/td>\n16.2.5.6 PMD DS port receive speed request (PMD_DSPORT_RXSPEED.request) and confirmation (PMD_DSPORT_RXSPEED.confirmation)
16.2.5.7 PMD DS port transmit data request (PMD_DSPORT_DATA.request)
16.2.5.8 PMD DS port transmit arbitration state request (PMD_DSPORT_ARB.request)
16.2.5.9 PMD DS port transmit speed request (PMD_DSPORT_TXSPEED.request) <\/td>\n<\/tr>\n
461<\/td>\n16.2.5.10 PMD DS port TpBias request (PMD_DSPORT_TPBIAS.request)
16.2.5.11 PMD cable power status request (PMD_PS.request) and confirmation (PMD_PS.confirmation)
16.2.5.12 PMD cable speed request (PMD_CABLE_SPEED.request) and confirmation (PMD_CABLE_SPEED.confirmation)
16.3 PHY facilities
16.3.1 PHY packet overview
16.3.1.1 PHY packet transmission and reception <\/td>\n<\/tr>\n
462<\/td>\n16.3.1.2 PHY packet identifier bits
16.3.2 Alpha packet formats <\/td>\n<\/tr>\n
463<\/td>\n16.3.2.1 Alpha self-ID packets <\/td>\n<\/tr>\n
465<\/td>\n16.3.2.2 Alpha Link-on packet
16.3.2.3 Alpha PHY configuration packet <\/td>\n<\/tr>\n
466<\/td>\n16.3.2.4 Alpha extended PHY packets
16.3.2.4.1 Alpha ping packet <\/td>\n<\/tr>\n
467<\/td>\n16.3.2.4.2 Alpha remote access packet
16.3.2.4.3 Alpha remote reply packet <\/td>\n<\/tr>\n
468<\/td>\n16.3.2.4.4 Alpha remote command packet <\/td>\n<\/tr>\n
469<\/td>\n16.3.2.4.5 Alpha remote confirmation packet <\/td>\n<\/tr>\n
470<\/td>\n16.3.2.4.6 Alpha resume packet
16.3.3 Beta PHY packet formats
16.3.3.1 Beta self-ID packets <\/td>\n<\/tr>\n
472<\/td>\n16.3.3.2 Beta Remote command packet <\/td>\n<\/tr>\n
473<\/td>\n16.3.3.3 Beta Remote confirmation packet <\/td>\n<\/tr>\n
474<\/td>\n16.3.3.4 Beta PHY configuration packet <\/td>\n<\/tr>\n
475<\/td>\n16.3.3.5 Loop test packet (LTP) <\/td>\n<\/tr>\n
476<\/td>\n16.3.4 Data packet formats
16.3.4.1 Alpha and Beta packet formats
16.3.4.2 General packet format <\/td>\n<\/tr>\n
477<\/td>\n16.3.4.3 Alpha format with speed code <\/td>\n<\/tr>\n
478<\/td>\n16.3.4.4 Alpha format for S100 packets without speed code <\/td>\n<\/tr>\n
479<\/td>\n16.3.4.5 Beta format for all packet speeds
16.3.4.6 Minimum packet spacing
16.3.4.7 Deletable symbols <\/td>\n<\/tr>\n
480<\/td>\n16.3.4.8 Packet transmission examples
16.3.4.8.1 Alpha S100 packet originated on S800 port of node with an Alpha link
16.3.4.8.2 Alpha S100 packet originated on S800 port of node with a Beta link
16.3.4.8.3 Alpha S200 packet originated on S800 port <\/td>\n<\/tr>\n
481<\/td>\n16.3.4.8.4 Beta S800 packet originated on S800 port
16.3.4.8.5 Beta S800 packet originated on S1600 port
16.3.5 Packet forwarding
16.3.5.1 Packets at speeds greater than the port operating speed
16.3.5.2 Packet forwarding: DS port to Beta port
16.3.5.3 Packet forwarding: Beta port to DS port <\/td>\n<\/tr>\n
482<\/td>\n16.4 Cable PHY operation
16.4.1 C code functions and variables <\/td>\n<\/tr>\n
484<\/td>\n16.4.2 Arbitration
16.4.2.1 DS-mode arbitration
16.4.2.2 Beta-mode arbitration <\/td>\n<\/tr>\n
485<\/td>\n16.4.2.2.1 Beta-mode requests <\/td>\n<\/tr>\n
486<\/td>\n16.4.2.2.2 Beta-mode grants <\/td>\n<\/tr>\n
487<\/td>\n16.4.3 Hybrid bus operation
16.4.3.1 Hybrid bus initialization <\/td>\n<\/tr>\n
488<\/td>\n16.4.3.2 Border node functions
16.4.3.2.1 Synchronization of gap events <\/td>\n<\/tr>\n
489<\/td>\n16.4.3.2.2 Protection of Alpha quiet windows <\/td>\n<\/tr>\n
490<\/td>\n16.4.3.2.3 BOSS PHYs unaware of isochronous interval
16.4.3.3 BORDER request mapping
16.4.3.3.1 Alpha to Beta
16.4.3.3.2 Beta to Alpha
16.4.3.4 Discussion of root outside the Beta cloud <\/td>\n<\/tr>\n
491<\/td>\n16.4.4 Isochronous intervals <\/td>\n<\/tr>\n
494<\/td>\n16.4.5 Bus reset state machine <\/td>\n<\/tr>\n
496<\/td>\n16.4.6 Tree identification state machine <\/td>\n<\/tr>\n
498<\/td>\n16.4.7 Self-identification state machine <\/td>\n<\/tr>\n
501<\/td>\n16.4.8 Arbitration state machine <\/td>\n<\/tr>\n
504<\/td>\n16.4.9 Large diameter networks
16.4.9.1 BOSS_RESTART_TIME <\/td>\n<\/tr>\n
505<\/td>\n16.4.9.2 TEST_INTERVAL <\/td>\n<\/tr>\n
507<\/td>\n17. Parallel PHY-link interface
17.1 Introduction <\/td>\n<\/tr>\n
508<\/td>\n17.2 Alpha (A) PHY-link interface specification <\/td>\n<\/tr>\n
511<\/td>\n17.2.1 Initialization and reset <\/td>\n<\/tr>\n
514<\/td>\n17.2.2 Link-on and interrupt indications
17.2.3 Link requests <\/td>\n<\/tr>\n
519<\/td>\n17.2.3.1 LReq rules <\/td>\n<\/tr>\n
522<\/td>\n17.2.3.2 Acceleration control
17.2.4 Status <\/td>\n<\/tr>\n
524<\/td>\n17.2.5 Transmit <\/td>\n<\/tr>\n
526<\/td>\n17.2.6 Cancel <\/td>\n<\/tr>\n
527<\/td>\n17.2.7 Receive
17.2.8 Electrical characteristics (cable environment)
17.2.8.1 DC signal levels and waveforms <\/td>\n<\/tr>\n
529<\/td>\n17.2.8.2 AC timing <\/td>\n<\/tr>\n
531<\/td>\n17.2.8.3 AC timing <\/td>\n<\/tr>\n
532<\/td>\n17.3 Beta (B) and Beta Plus (B Plus) PHY-link interface specification <\/td>\n<\/tr>\n
533<\/td>\n17.3.1 Beta (B) and Beta Plus (B Plus) PHY-link interface characteristics
17.3.2 PHY-link interface signals
17.3.2.1 PHY signals
17.3.2.2 Link signals <\/td>\n<\/tr>\n
534<\/td>\n17.3.2.3 PHY-Link signal descriptions <\/td>\n<\/tr>\n
535<\/td>\n17.3.2.4 Detailed signal descriptions <\/td>\n<\/tr>\n
536<\/td>\n17.3.2.5 Differentiated signals <\/td>\n<\/tr>\n
537<\/td>\n17.3.3 Interface initialization, reset, and disable
17.3.3.1 LPS signal characteristics <\/td>\n<\/tr>\n
538<\/td>\n17.3.3.2 Interface reset <\/td>\n<\/tr>\n
539<\/td>\n17.3.3.3 Interface disable <\/td>\n<\/tr>\n
540<\/td>\n17.3.3.4 Restoration and initialization
17.3.3.5 Initialization completion sequence <\/td>\n<\/tr>\n
541<\/td>\n17.3.4 LinkOn signal characteristics <\/td>\n<\/tr>\n
542<\/td>\n17.3.5 Link requests and notifications <\/td>\n<\/tr>\n
543<\/td>\n17.3.5.1 Link request characteristics
17.3.5.1.1 Asynchronous packet transmit requests <\/td>\n<\/tr>\n
544<\/td>\n17.3.5.1.2 Cycle Start packet transmit requests
17.3.5.1.3 Immediate packet transmit requests <\/td>\n<\/tr>\n
545<\/td>\n17.3.5.1.4 Isochronous packet transmit requests
17.3.5.1.5 Register Access read or write requests <\/td>\n<\/tr>\n
546<\/td>\n17.3.5.1.6 Restore
17.3.5.2 Link notifications
17.3.5.2.1 Cycle start received notification
17.3.5.2.2 Cycle start due notification <\/td>\n<\/tr>\n
547<\/td>\n17.3.5.3 Link request and notification format <\/td>\n<\/tr>\n
550<\/td>\n17.3.6 Interface data transfers
17.3.6.1 Interface phases
17.3.6.2 Packet reception <\/td>\n<\/tr>\n
551<\/td>\n17.3.6.2.1 Packet reception operation
17.3.6.2.2 Packet reception timing <\/td>\n<\/tr>\n
552<\/td>\n17.3.6.2.3 Packet reception description <\/td>\n<\/tr>\n
553<\/td>\n17.3.6.2.4 Interpacket spacing for received packets
17.3.6.3 Packet transmission <\/td>\n<\/tr>\n
554<\/td>\n17.3.6.3.1 Packet transmit operation
17.3.6.3.2 PHY-link packet transmit timing <\/td>\n<\/tr>\n
557<\/td>\n17.3.6.3.3 PHY-link packet transmission description <\/td>\n<\/tr>\n
558<\/td>\n17.3.6.3.4 Transmit grant types <\/td>\n<\/tr>\n
559<\/td>\n17.3.6.3.5 Additional information encoding <\/td>\n<\/tr>\n
560<\/td>\n17.3.7 Format of received and transmitted data <\/td>\n<\/tr>\n
561<\/td>\n17.3.7.1 S100 data <\/td>\n<\/tr>\n
562<\/td>\n17.3.7.2 S200 data
17.3.7.3 S400 data <\/td>\n<\/tr>\n
563<\/td>\n17.3.7.4 S800 data <\/td>\n<\/tr>\n
564<\/td>\n17.3.7.5 S1600 Data
17.3.7.6 S3200 Data
17.3.8 Status transfers and notifications from the PHY <\/td>\n<\/tr>\n
565<\/td>\n17.3.8.1 Bus Status Transfers
17.3.8.1.1 Serial bus reset indications <\/td>\n<\/tr>\n
566<\/td>\n17.3.8.1.2 Bus Status Transfer format
17.3.8.2 PHY Status Transfers <\/td>\n<\/tr>\n
567<\/td>\n17.3.8.2.1 PHY Interrupt indications
17.3.8.2.2 PHY Register Read indications
17.3.8.2.3 Bus Initialization indications
17.3.8.2.4 PHY Status Transfer format <\/td>\n<\/tr>\n
569<\/td>\n17.3.9 Delays affecting interoperability of PHYs and links
17.3.10 Alpha link support <\/td>\n<\/tr>\n
570<\/td>\n17.3.11 Electrical characteristics
17.3.11.1 DC signal levels and waveforms <\/td>\n<\/tr>\n
572<\/td>\n17.3.11.2 AC timing <\/td>\n<\/tr>\n
575<\/td>\n17.4 Isolation barrier
17.4.1 Introduction
17.4.2 Capacitive isolation barrier <\/td>\n<\/tr>\n
578<\/td>\n17.4.3 Alternative isolation barrier <\/td>\n<\/tr>\n
581<\/td>\n18. PIL-FOP serial interface
18.1 Operating model <\/td>\n<\/tr>\n
582<\/td>\n18.2 PIL-FOP connection management
18.2.1 Power-on
18.2.2 PIL-FOP negotiation <\/td>\n<\/tr>\n
583<\/td>\n18.2.3 PIL-FOP restore
18.2.4 Port restore
18.2.5 Loss of synchronization
18.2.6 Loss of power <\/td>\n<\/tr>\n
584<\/td>\n18.2.7 LPS
18.2.8 Serial bus reset
18.3 Serial bus configuration request types not carried over the PIL-FOP interface
18.4 P2P packet protocol <\/td>\n<\/tr>\n
587<\/td>\n19. PHY C code
19.1 Common declarations and functions <\/td>\n<\/tr>\n
606<\/td>\n19.2 Connection management routines
19.2.1 Node-level connection monitor <\/td>\n<\/tr>\n
615<\/td>\n19.2.2 Port connection manager actions and conditions <\/td>\n<\/tr>\n
635<\/td>\n19.3 Port state machine actions <\/td>\n<\/tr>\n
636<\/td>\n19.3.1 DS port <\/td>\n<\/tr>\n
643<\/td>\n19.3.2 Beta port <\/td>\n<\/tr>\n
659<\/td>\n19.3.3 T-mode port <\/td>\n<\/tr>\n
678<\/td>\n19.4 Border arbitration actions and conditions
19.4.1 Border arbitration functions <\/td>\n<\/tr>\n
702<\/td>\n19.4.2 Request processing <\/td>\n<\/tr>\n
712<\/td>\n19.4.3 Bus reset <\/td>\n<\/tr>\n
715<\/td>\n19.4.4 Tree identification <\/td>\n<\/tr>\n
716<\/td>\n19.4.5 Self-identification <\/td>\n<\/tr>\n
721<\/td>\n19.5 Border arbitration <\/td>\n<\/tr>\n
737<\/td>\n20. T-mode port specification
20.1 Overview <\/td>\n<\/tr>\n
738<\/td>\n20.2 Port functions
20.2.1 Port functions overview
20.2.2 Adaptation <\/td>\n<\/tr>\n
739<\/td>\n20.2.2.1 Rate adaptation
20.2.2.2 Clause 40 in IEEE Std 802.3-2005 <\/td>\n<\/tr>\n
740<\/td>\n20.2.3 Coding
20.2.3.1 Main properties <\/td>\n<\/tr>\n
741<\/td>\n20.2.4 Symbol types
20.2.5 Data symbols
20.2.6 Arbitration requests <\/td>\n<\/tr>\n
743<\/td>\n20.2.7 Configuration requests
20.2.8 Control symbols in symbol positions A and B
20.2.9 Control symbols in symbol positions C and D <\/td>\n<\/tr>\n
744<\/td>\n20.3 T-mode port operation
20.3.1 Transmit operations
20.3.1.1 Control transmission <\/td>\n<\/tr>\n
745<\/td>\n20.3.1.2 Request transmission
20.3.1.3 Packet transmission
20.3.1.4 Speed signaling
20.3.1.5 Payload transmission <\/td>\n<\/tr>\n
747<\/td>\n20.3.2 Receive operations
20.3.2.1 Symbol decode rules <\/td>\n<\/tr>\n
749<\/td>\n20.3.2.1.1 Loss of synchronization detection procedure <\/td>\n<\/tr>\n
750<\/td>\n20.3.2.2 Control reception
20.3.2.3 Request type reception
20.3.2.4 Speed code determination <\/td>\n<\/tr>\n
751<\/td>\n20.3.2.5 Payload reception
20.3.2.6 Further robustness measures <\/td>\n<\/tr>\n
752<\/td>\n20.3.2.7 Error reporting <\/td>\n<\/tr>\n
753<\/td>\n21. S800 UTP (T-mode) PMD electrical specification <\/td>\n<\/tr>\n
754<\/td>\n21.1 T-mode PMD specification
21.2 T-mode PMD initialization
21.3 Gigabit media independent interface (GMII) <\/td>\n<\/tr>\n
755<\/td>\n21.4 T-mode suspend and resume
21.4.1 Alternative link pulse (ALP)
21.4.2 Suspend
21.4.3 Resume <\/td>\n<\/tr>\n
756<\/td>\n21.5 UTP cable power <\/td>\n<\/tr>\n
757<\/td>\nAnnex A (normative) Cable environment electrical isolation
A.1 Grounding characteristics of ac-powered devices
A.2 Electrical isolation <\/td>\n<\/tr>\n
758<\/td>\nA.3 Agency requirements <\/td>\n<\/tr>\n
761<\/td>\nAnnex B (normative) External connector positive retention <\/td>\n<\/tr>\n
763<\/td>\nAnnex C (normative) Internal device physical interface
C.1 Overview
C.2 Electrical interface for internal devices
C.2.1 Power requirements <\/td>\n<\/tr>\n
764<\/td>\nC.2.2 Bus signal requirements <\/td>\n<\/tr>\n
765<\/td>\nC.2.3 Miscellaneous signals
C.2.4 Signal descriptions <\/td>\n<\/tr>\n
767<\/td>\nC.3 Internal unitized device connectors <\/td>\n<\/tr>\n
769<\/td>\nC.3.1 Internal unitized plug <\/td>\n<\/tr>\n
775<\/td>\nC.3.2 Internal unitized receptacles <\/td>\n<\/tr>\n
779<\/td>\nC.3.3 Connector cable receptacles <\/td>\n<\/tr>\n
782<\/td>\nC.3.4 Cable receptacle termination
C.3.5 Cable <\/td>\n<\/tr>\n
783<\/td>\nC.3.6 Contact finish on mating surfaces of plug and receptacle contacts
C.3.7 Termination finish on plug and receptacle contact
C.3.8 Connector performance criteria <\/td>\n<\/tr>\n
791<\/td>\nAnnex D (normative) Backplane PHY timing formulas
D.1 Backplane propagation delay <\/td>\n<\/tr>\n
792<\/td>\nD.2 Backplane arbitration timing
D.2.1 Synchronization timing <\/td>\n<\/tr>\n
793<\/td>\nD.2.2 Arbitration sample timing
D.2.3 Arbitration hold timing <\/td>\n<\/tr>\n
794<\/td>\nD.2.4 Arbitration bit timing
D.3 Backplane gap timing <\/td>\n<\/tr>\n
795<\/td>\nD.3.1 Acknowledge gap <\/td>\n<\/tr>\n
796<\/td>\nD.3.2 Subaction gap and arbitration reset gap <\/td>\n<\/tr>\n
797<\/td>\nD.3.3 Arbitration gap scenarios <\/td>\n<\/tr>\n
800<\/td>\nD.4 Backplane environment skew <\/td>\n<\/tr>\n
801<\/td>\nAnnex E (normative) Cable operation and implementation examples
E.1 Performance optimization <\/td>\n<\/tr>\n
805<\/td>\nE.2 Cable environment jitter budget <\/td>\n<\/tr>\n
807<\/td>\nE.3 Cable PHY configuration example
E.3.1 Bus initialization process
E.3.2 Tree identify process <\/td>\n<\/tr>\n
811<\/td>\nE.3.3 Self identify process <\/td>\n<\/tr>\n
817<\/td>\nE.3.4 Topology construction <\/td>\n<\/tr>\n
821<\/td>\nAnnex F (normative) Backplane physical implementation example
F.1 Standardized parallel bus implementations <\/td>\n<\/tr>\n
823<\/td>\nF.2 PHY implementation
F.2.1 PHY layer overview <\/td>\n<\/tr>\n
824<\/td>\nF.2.2 High-level PHY logic description <\/td>\n<\/tr>\n
827<\/td>\nAnnex G (normative) Backplane IRM selection
G.1 Backplane configuration management
G.2 IRM selection process
G.3 Example of an IRM selection process
G.3.1 IRM-capable node environment <\/td>\n<\/tr>\n
828<\/td>\nG.3.2 Non-IRM environment <\/td>\n<\/tr>\n
829<\/td>\nAnnex H (normative) Serial bus configuration in the cable environment
H.1 Bus configuration timeline <\/td>\n<\/tr>\n
830<\/td>\nH.2 Bus configuration scenarios
H.2.1 Bus configuration with a bus manager and an IRM <\/td>\n<\/tr>\n
834<\/td>\nH.2.2 Bus configuration with only an IRM <\/td>\n<\/tr>\n
835<\/td>\nH.3 Combined bus manager and IRM <\/td>\n<\/tr>\n
836<\/td>\nH.4 Abdication by the bus manager <\/td>\n<\/tr>\n
837<\/td>\nAnnex I (normative) Socket PCB terminal patterns and mounting
I.1 Socket orientation
I.2 PCB mounting 0 <\/td>\n<\/tr>\n
843<\/td>\nAnnex J (normative) Transaction integrity safeguards <\/td>\n<\/tr>\n
845<\/td>\nAnnex K (normative) Serial bus cable assembly test procedures
K.1 Scope
K.2 Test fixtures
K.2.1 Cable test fixture <\/td>\n<\/tr>\n
847<\/td>\nK.2.2 Differential test fixture <\/td>\n<\/tr>\n
849<\/td>\nK.3 Signal pairs characteristic and discrete impedance <\/td>\n<\/tr>\n
850<\/td>\nK.3.1 Signal pairs impedance setup calibration-short and load
K.3.2 Signal pairs impedance test procedure (connector) <\/td>\n<\/tr>\n
851<\/td>\nK.3.3 Signal pairs impedance limits (connector)
K.3.4 IEEE 1394 bulk serial bus cable test methodology <\/td>\n<\/tr>\n
852<\/td>\nK.4 Signal pairs attenuation
K.4.1 Signal pairs attenuation setup calibration <\/td>\n<\/tr>\n
853<\/td>\nK.4.2 ATPA <\/td>\n<\/tr>\n
854<\/td>\nK.4.3 ATPB <\/td>\n<\/tr>\n
855<\/td>\nK.4.4 Signal pairs attenuation limits
K.4.5 IEEE 1394 bulk serial bus cable test methodology
K.5 Signal pairs velocity of propagation <\/td>\n<\/tr>\n
856<\/td>\nK.5.1 Signal pairs velocity of propagation setup calibration
K.5.2 VTPA <\/td>\n<\/tr>\n
857<\/td>\nK.5.3 VTPB
K.5.4 Signal pairs velocity of propagation limits
K.5.5 IEEE 1394 bulk serial bus cable test methodology (TDR) <\/td>\n<\/tr>\n
858<\/td>\nK.5.6 IEEE 1394 bulk serial bus cable test methodology (frequency sweep)
K.5.7 Rise and fall time <\/td>\n<\/tr>\n
859<\/td>\nK.5.8 Static shield isolation (insulation resistance)
K.6 Signal pairs relative propagation skew <\/td>\n<\/tr>\n
860<\/td>\nK.6.1 Signal pairs skew setup calibration <\/td>\n<\/tr>\n
861<\/td>\nK.6.2 Signal pairs skew test procedure
K.6.3 Signal pairs skew limits <\/td>\n<\/tr>\n
862<\/td>\nK.7 Power pair characteristic impedance <\/td>\n<\/tr>\n
863<\/td>\nK.7.1 Power pair impedance setup calibration-short and load
K.7.2 Power pair impedance test procedure
K.7.3 Power pair dc resistance <\/td>\n<\/tr>\n
864<\/td>\nK.7.4 DC resistance setup calibration <\/td>\n<\/tr>\n
865<\/td>\nK.7.5 DC resistance test procedure
K.7.6 DC resistance limits <\/td>\n<\/tr>\n
866<\/td>\nK.8 Crosstalk
K.8.1 Crosstalk setup calibration <\/td>\n<\/tr>\n
867<\/td>\nK.8.2 Crosstalk test procedure (between power and signal pairs) <\/td>\n<\/tr>\n
868<\/td>\nK.8.3 Crosstalk test procedure (between signal pairs)
K.8.4 Crosstalk limits <\/td>\n<\/tr>\n
869<\/td>\nK.8.5 Crosstalk limits (between signal pairs) <\/td>\n<\/tr>\n
871<\/td>\nAnnex L (normative) Shielding effectiveness and transfer impedance testing
L.1 Content
L.2 Definitions
L.3 Test equipment <\/td>\n<\/tr>\n
872<\/td>\nL.4 Theory
L.4.1 Reference measurement
L.4.2 Sample measurement <\/td>\n<\/tr>\n
873<\/td>\nL.4.3 Calculations
L.5 Sample preparation
L.5.1 Panel-mounted connector sample <\/td>\n<\/tr>\n
874<\/td>\nL.5.2 Measure sample Zo with TDR
L.5.3 Cable-mounted connector sample
L.6 Procedure <\/td>\n<\/tr>\n
875<\/td>\nL.7 \u201cNoise floor\u201d plot
L.8 Documentation
L.8.1 Plots and magnetic files <\/td>\n<\/tr>\n
876<\/td>\nL.8.2 Test report
L.9 Performance <\/td>\n<\/tr>\n
877<\/td>\nAnnex M (informative) Serial bus topology considerations for power distribution (cable environment) <\/td>\n<\/tr>\n
881<\/td>\nAnnex N (normative) Jitter measurements
N.1 Test patterns
N.2 Random pattern (SB_RPAT)
N.3 Receive jitter tolerance pattern (SB_JTPAT) <\/td>\n<\/tr>\n
882<\/td>\nN.4 Supply noise test sequence (SB_SPAT) <\/td>\n<\/tr>\n
883<\/td>\nAnnex O (informative) Connection status change <\/td>\n<\/tr>\n
885<\/td>\nAnnex P (informative) Deriving bus topology from self-ID packets
P.1 Bus topology analysis <\/td>\n<\/tr>\n
886<\/td>\nP.2 Topology analysis after power reset <\/td>\n<\/tr>\n
890<\/td>\nP.3 Topology analysis when the root changes <\/td>\n<\/tr>\n
892<\/td>\nP.4 Topology analysis when a node is inserted <\/td>\n<\/tr>\n
895<\/td>\nAnnex Q (informative) Summary description
Q.1 Node and module architectures <\/td>\n<\/tr>\n
896<\/td>\nQ.2 Topology
Q.2.1 Cable environment <\/td>\n<\/tr>\n
897<\/td>\nQ.2.2 Backplane environment
Q.3 Addressing <\/td>\n<\/tr>\n
898<\/td>\nQ.4 Protocol architecture and data transfer services
Q.4.1 SBP architecture
Q.4.2 Data transfer services <\/td>\n<\/tr>\n
899<\/td>\nQ.5 Transaction layer <\/td>\n<\/tr>\n
900<\/td>\nQ.5.1 Transaction layer services
Q.5.2 Lock subcommands <\/td>\n<\/tr>\n
901<\/td>\nQ.5.3 Subaction queue independence <\/td>\n<\/tr>\n
902<\/td>\nQ.6 Link layer <\/td>\n<\/tr>\n
903<\/td>\nQ.6.1 Link layer services <\/td>\n<\/tr>\n
904<\/td>\nQ.6.2 Link and transaction layer interactions <\/td>\n<\/tr>\n
907<\/td>\nQ.6.3 Asynchronous arbitration <\/td>\n<\/tr>\n
908<\/td>\nQ.6.4 Isochronous arbitration <\/td>\n<\/tr>\n
909<\/td>\nQ.7 Physical layer (PHY)
Q.7.1 Data bit transmission and reception <\/td>\n<\/tr>\n
910<\/td>\nQ.7.2 Fair arbitration <\/td>\n<\/tr>\n
911<\/td>\nQ.7.3 Cable PHY <\/td>\n<\/tr>\n
919<\/td>\nQ.7.4 Backplane PHY <\/td>\n<\/tr>\n
922<\/td>\nQ.8 Bus management
Q.9 New features of IEEE Std 1394a-2000 <\/td>\n<\/tr>\n
923<\/td>\nQ.9.1 Connection debounce
Q.9.2 Cable arbitration enhancements <\/td>\n<\/tr>\n
927<\/td>\nQ.9.3 Performance optimization via PHY \u201cpinging\u201d
Q.9.4 Priority arbitration <\/td>\n<\/tr>\n
928<\/td>\nQ.9.5 Port disable, suspend, and resume <\/td>\n<\/tr>\n
931<\/td>\nQ.10 New features of IEEE Std 1394b-2002
Q.10.1 The relationship to IEEE Std 1394a-2000
Q.10.2 Faster and further <\/td>\n<\/tr>\n
932<\/td>\nQ.10.3 Nomenclature <\/td>\n<\/tr>\n
933<\/td>\nQ.10.4 Media-common properties <\/td>\n<\/tr>\n
934<\/td>\nQ.10.5 Arbitration improvements <\/td>\n<\/tr>\n
940<\/td>\nQ.10.6 PHY-link interface <\/td>\n<\/tr>\n
941<\/td>\nQ.10.7 Miscellaneous features <\/td>\n<\/tr>\n
942<\/td>\nQ.11 New features of IEEE Std 1394c-2006
Q.11.1 Scope <\/td>\n<\/tr>\n
943<\/td>\nQ.11.2 Purpose
Q.11.3 T-mode features
Q.11.4 The relationship of T-mode to Beta mode
Q.11.5 The relationship to IEEE Std 802.3-2005
Q.11.6 S800 over UTP <\/td>\n<\/tr>\n
944<\/td>\nQ.11.7 Twin-mode ports
Q.12 New features of IEEE Std 1394-2008
Q.12.1 Errata
Q.12.2 Enhanced UTP PMD <\/td>\n<\/tr>\n
945<\/td>\nQ.12.3 Beta PMD electrical specification
Q.12.4 Beta Plus PHY-link interface
Q.12.5 Bus topology determination
Q.12.6 Document organization <\/td>\n<\/tr>\n
947<\/td>\nAnnex R (informative) Glossary
R.1 Conformance
R.2 Definitions <\/td>\n<\/tr>\n
953<\/td>\nAnnex S (informative) Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for a High-Performance Serial Bus<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2008<\/td>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":399574,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-399568","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/399568","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/399574"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=399568"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=399568"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=399568"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}