{"id":398052,"date":"2024-10-20T04:33:39","date_gmt":"2024-10-20T04:33:39","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-802-3bj-2014-2\/"},"modified":"2024-10-26T08:21:52","modified_gmt":"2024-10-26T08:21:52","slug":"ieee-802-3bj-2014-2","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-802-3bj-2014-2\/","title":{"rendered":"IEEE 802.3bj-2014"},"content":{"rendered":"

Amendment Standard – Superseded. 100 Gb\/s Physical Layer (PHY) specifications and management parameters for operation on electrical backplanes and twinaxial copper cables are added by this amendment to IEEE Std 802.3-2012. This amendment also specifies optional Energy Efficient Ethernet (EEE) for 40 Gb\/s and 100 Gb\/s operation over electrical backplanes and copper cables.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Std 802.3bj-2014 Front cover <\/td>\n<\/tr>\n
3<\/td>\nTitle page <\/td>\n<\/tr>\n
4<\/td>\nAbstract\/Keywords <\/td>\n<\/tr>\n
5<\/td>\nImportant Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n
8<\/td>\nParticipants <\/td>\n<\/tr>\n
12<\/td>\nIntroduction <\/td>\n<\/tr>\n
15<\/td>\nContents <\/td>\n<\/tr>\n
33<\/td>\nIMPORTANT NOTICE <\/td>\n<\/tr>\n
34<\/td>\n1. Introduction
1.4 Definitions <\/td>\n<\/tr>\n
35<\/td>\n1.5 Abbreviations <\/td>\n<\/tr>\n
36<\/td>\n30. Management
30.2 Managed objects
30.2.5 Capabilities <\/td>\n<\/tr>\n
38<\/td>\n30.3 Layer management for DTEs
30.3.2.1.2 aPhyType
30.3.2.1.3 aPhyTypeList
30.5 Layer management for medium attachment units (MAUs)
30.5.1.1.2 aMAUType <\/td>\n<\/tr>\n
39<\/td>\n30.5.1.1.11 aBIPErrorCount
30.5.1.1.12 aLaneMapping
30.5.1.1.15 aFECability
30.5.1.1.16 aFECmode <\/td>\n<\/tr>\n
40<\/td>\n30.5.1.1.17 aFECCorrectedBlocks
30.5.1.1.18 aFECUncorrectableBlocks <\/td>\n<\/tr>\n
41<\/td>\n30.5.1.1.26 aRSFECBIPErrorCount
30.5.1.1.27 aRSFECLaneMapping
30.5.1.1.28 aRSFECBypassAbility <\/td>\n<\/tr>\n
42<\/td>\n30.5.1.1.29 aRSFECIndicationAbility
30.5.1.1.30 aRSFECBypassEnable
30.5.1.1.31 aRSFECIndicationEnable <\/td>\n<\/tr>\n
43<\/td>\n30.6 Management for link Auto-Negotiation
30.6.1.1.5 aAutoNegLocalTechnologyAbility <\/td>\n<\/tr>\n
44<\/td>\n30.12 Layer Management for Link Layer Discovery Protocol (LLDP)
30.12.2 LLDP Local System Group managed object class
30.12.2.1 LLDP Local System Group attributes
30.12.2.1.30 aLldpXdot3LocTxFw
30.12.2.1.31 aLldpXdot3LocTxFwEcho
30.12.2.1.32 aLldpXdot3LocRxFw
30.12.2.1.33 aLldpXdot3LocRxFwEcho <\/td>\n<\/tr>\n
45<\/td>\n30.12.3 LLDP Remote System Group managed object class
30.12.3.1 LLDP Remote System Group attributes
30.12.3.1.24 aLldpXdot3RemTxFw
30.12.3.1.25 aLldpXdot3RemTxFwEcho
30.12.3.1.26 aLldpXdot3RemRxFw
30.12.3.1.27 aLldpXdot3RemRxFwEcho <\/td>\n<\/tr>\n
46<\/td>\n45. Management Data Input\/Output (MDIO) Interface
45.2.1 PMA\/PMD registers <\/td>\n<\/tr>\n
47<\/td>\n45.2.1.2 PMA\/PMD status 1 register (Register 1.1) <\/td>\n<\/tr>\n
48<\/td>\n45.2.1.2.a PMA ingress AUI stop ability (1.1.9)
45.2.1.2.b PMA egress AUI stop ability (1.1.8)
45.2.1.6 PMA\/PMD control 2 register (Register 1.7) <\/td>\n<\/tr>\n
50<\/td>\n45.2.1.6.a PMA ingress AUI stop enable (1.7.9)
45.2.1.6.b PMA egress AUI stop enable (1.7.8)
45.2.1.7.4 Transmit fault (1.8.11)
45.2.1.7.5 Receive fault (1.8.10)
45.2.1.8 PMD transmit disable register (Register 1.9) <\/td>\n<\/tr>\n
52<\/td>\n45.2.1.12 40G\/100G PMA\/PMD extended ability register (Register 1.13)
45.2.1.12.1a 100GBASE-CR4 ability (1.13.14)
45.2.1.12.1b 100GBASE-KR4 ability (1.13.13)
45.2.1.12.1c 100GBASE-KP4 ability (1.13.12)
45.2.1.13a EEE capability (Register 1.16) <\/td>\n<\/tr>\n
53<\/td>\n45.2.1.13a.1 100GBASE-CR4 EEE deep sleep supported (1.16.11)
45.2.1.13a.2 100GBASE-KR4 EEE deep sleep supported (1.16.10)
45.2.1.13a.3 100GBASE-KP4 EEE deep sleep supported (1.16.9)
45.2.1.13a.4 100GBASE-CR10 EEE deep sleep supported (1.16.8)
45.2.1.13a.5 40GBASE-CR4 EEE deep sleep supported (1.16.1)
45.2.1.13a.6 40GBASE-KR4 EEE deep sleep supported (1.16.0) <\/td>\n<\/tr>\n
54<\/td>\n45.2.1.79 BASE-R PMD control register (Register 1.150)
45.2.1.80 BASE-R PMD status register (Register 1.151)
45.2.1.81 BASE-R LP coefficient update, lane 0 register (Register 1.152)
45.2.1.82 BASE-R LP status report, lane 0 register (Register 1.153)
45.2.1.83 BASE-R LD coefficient update, lane 0 register (Register 1.154)
45.2.1.84 BASE-R LD status report, lane 0 register (Register 1.155) <\/td>\n<\/tr>\n
55<\/td>\n45.2.1.88a PMA overhead control 1, 2, and 3 registers (Register 1.162 through 1.164)
45.2.1.88b PMA overhead status 1 and 2 registers (Register 1.165, 1.166) <\/td>\n<\/tr>\n
56<\/td>\n45.2.1.92a RS-FEC control register (Register 1.200)
45.2.1.92a.1 FEC bypass indication enable (1.200.1)
45.2.1.92a.2 FEC bypass correction enable (1.200.0) <\/td>\n<\/tr>\n
57<\/td>\n45.2.1.92b RS-FEC status register (Register 1.201)
45.2.1.92b.1 PCS align status (1.201.15)
45.2.1.92b.2 RS-FEC align status (1.201.14) <\/td>\n<\/tr>\n
58<\/td>\n45.2.1.92b.3 FEC AM lock 3 (1.201.11)
45.2.1.92b.4 FEC AM lock 2 (1.201.10)
45.2.1.92b.5 FEC AM lock 1 (1.201.9)
45.2.1.92b.6 FEC AM lock 0 (1.201.8)
45.2.1.92b.7 RS-FEC high SER (1.201.2)
45.2.1.92b.8 FEC bypass indication ability (1.201.1)
45.2.1.92b.9 FEC bypass correction ability (1.201.0)
45.2.1.92c RS-FEC corrected codewords counter (Register 1.202, 1.203) <\/td>\n<\/tr>\n
59<\/td>\n45.2.1.92d RS-FEC uncorrected codewords counter (Register 1.204, 1.205)
45.2.1.92e RS-FEC lane mapping register (Register 1.206) <\/td>\n<\/tr>\n
60<\/td>\n45.2.1.92f RS-FEC symbol error counter lane 0 (Register 1.210, 1.211)
45.2.1.92g RS-FEC symbol error counter lane 1 through 3 (Register 1.212, 1.213, 1.214, 1.215, 1.216, 1.217)
45.2.1.92h RS-FEC BIP error counter lane 0 (Register 1.230)
45.2.1.92i RS-FEC BIP error counter, lane 1 through 19 (Registers 1.231 through 1.249) <\/td>\n<\/tr>\n
61<\/td>\n45.2.1.92j RS-FEC PCS lane 0 mapping register (Register 1.250)
45.2.1.92k RS-FEC PCS lanes 1 through 19 mapping registers (Registers 1.251 through 1.269)
45.2.1.92l RS-FEC PCS alignment status 1 register (Register 1.280) <\/td>\n<\/tr>\n
62<\/td>\n45.2.1.92l.1 Block 7 lock (1.280.7)
45.2.1.92l.2 Block 6 lock (1.280.6)
45.2.1.92l.3 Block 5 lock (1.280.5)
45.2.1.92l.4 Block 4 lock (1.280.4)
45.2.1.92l.5 Block 3 lock (1.280.3) <\/td>\n<\/tr>\n
63<\/td>\n45.2.1.92l.6 Block 2 lock (1.280.2)
45.2.1.92l.7 Block 1 lock (1.280.1)
45.2.1.92l.8 Block 0 lock (1.280.0)
45.2.1.92m RS-FEC PCS alignment status 2 register (Register 1.281) <\/td>\n<\/tr>\n
64<\/td>\n45.2.1.92m.1 Block 19 lock (1.281.11)
45.2.1.92m.2 Block 18 lock (1.281.10)
45.2.1.92m.3 Block 17 lock (1.281.9)
45.2.1.92m.4 Block 16 lock (1.281.8)
45.2.1.92m.5 Block 15 lock (1.281.7)
45.2.1.92m.6 Block 14 lock (1.281.6) <\/td>\n<\/tr>\n
65<\/td>\n45.2.1.92m.7 Block 13 lock (1.281.5)
45.2.1.92m.8 Block 12 lock (1.281.4)
45.2.1.92m.9 Block 11 lock (1.281.3)
45.2.1.92m.10 Block 10 lock (1.281.2)
45.2.1.92m.11 Block 9 lock (1.281.1)
45.2.1.92m.12 Block 8 lock (1.281.0)
45.2.1.92n RS-FEC PCS alignment status 3 register (Register 1.282)
45.2.1.92n.1 Lane 7 aligned (1.282.7) <\/td>\n<\/tr>\n
66<\/td>\n45.2.1.92n.2 Lane 6 aligned (1.282.6)
45.2.1.92n.3 Lane 5 aligned (1.282.5)
45.2.1.92n.4 Lane 4 aligned (1.282.4)
45.2.1.92n.5 Lane 3 aligned (1.282.3) <\/td>\n<\/tr>\n
67<\/td>\n45.2.1.92n.6 Lane 2 aligned (1.282.2)
45.2.1.92n.7 Lane 1 aligned (1.282.1)
45.2.1.92n.8 Lane 0 aligned (1.282.0)
45.2.1.92o RS-FEC PCS alignment status 4 register (Register 1.283) <\/td>\n<\/tr>\n
68<\/td>\n45.2.1.92o.1 Lane 19 aligned (1.283.11)
45.2.1.92o.2 Lane 18 aligned (1.283.10)
45.2.1.92o.3 Lane 17 aligned (1.283.9)
45.2.1.92o.4 Lane 16 aligned (1.283.8)
45.2.1.92o.5 Lane 15 aligned (1.283.7) <\/td>\n<\/tr>\n
69<\/td>\n45.2.1.92o.6 Lane 14 aligned (1.283.6)
45.2.1.92o.7 Lane 13 aligned (1.283.5)
45.2.1.92o.8 Lane 12 aligned (1.283.4)
45.2.1.92o.9 Lane 11 aligned (1.283.3)
45.2.1.92o.10 Lane 10 aligned (1.283.2)
45.2.1.92o.11 Lane 9 aligned (1.283.1)
45.2.1.92o.12 Lane 8 aligned (1.283.0)
45.2.1.98a PMD training pattern lanes 0 through 3 (Register 1.1450 through 1.1453) <\/td>\n<\/tr>\n
70<\/td>\n45.2.1.100 PRBS pattern testing control (Register 1.1501) <\/td>\n<\/tr>\n
71<\/td>\n45.2.3 PCS registers
45.2.3.9 EEE control and capability (Register 3.20) <\/td>\n<\/tr>\n
72<\/td>\n45.2.3.9.a 100GBASE-R EEE deep sleep supported (3.20.13)
45.2.3.9.b 100GBASE-R EEE fast wake supported (3.20.12)
45.2.3.9.c 40GBASE-R EEE deep sleep supported (3.20.9)
45.2.3.9.d 40GBASE-R EEE fast wake supported (3.20.8)
45.2.3.9.7 LPI_FW (3.20.0)
45.2.7 Auto-Negotiation registers
45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48) <\/td>\n<\/tr>\n
73<\/td>\n45.2.7.12.2 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8, 7.48.9, 7.48.10, 7.48.11)
45.2.7.13 EEE advertisement (Register 7.60) <\/td>\n<\/tr>\n
75<\/td>\n45.2.7.13.a 100GBASE-CR4 EEE supported (7.60.13)
45.2.7.13.b 100GBASE-KR4 EEE supported (7.60.12)
45.2.7.13.c 100GBASE-KP4 EEE supported (7.60.11)
45.2.7.13.d 100GBASE-CR10 EEE supported (7.60.10)
45.2.7.13.e 40GBASE-CR4 EEE supported (7.60.8)
45.2.7.13.f 40GBASE-KR4 EEE supported (7.60.7)
45.2.7.14 EEE link partner ability (Register 7.61) <\/td>\n<\/tr>\n
77<\/td>\n45.5 Protocol implementation conformance statement (PICS) proforma for Clause 45, Management Data Input\/Output (MDIO) Interface
45.5.3.2 PMA\/PMD MMD options
45.5.3.3 PMA\/PMD management functions <\/td>\n<\/tr>\n
78<\/td>\n69. Introduction to Ethernet operation over electrical backplanes
69.1 Overview
69.1.1 Scope
69.1.2 Objectives
69.1.2 Relationship of Backplane Ethernet to the ISO OSI reference model <\/td>\n<\/tr>\n
80<\/td>\n69.2 Summary of Backplane Ethernet Sublayers
69.2.1 Reconciliation sublayer and media independent interfaces <\/td>\n<\/tr>\n
81<\/td>\n69.2.3 Physical Layer signaling systems <\/td>\n<\/tr>\n
82<\/td>\n69.2.6 Low-Power Idle
69.3 Delay constraints
69.5 Protocol implementation conformance statement (PICS) proforma <\/td>\n<\/tr>\n
83<\/td>\n73. Auto-Negotiation for backplane and copper cable assembly
73.3 Functional specifications
73.5 DME transmission
73.5.1 DME electrical specifications
73.6 Link codeword encoding
73.6.4 Technology Ability Field <\/td>\n<\/tr>\n
84<\/td>\n73.6.10 Transmit Switch function
73.7 Receive function requirements
73.7.1 DME page reception
73.7.2 Receive Switch function <\/td>\n<\/tr>\n
85<\/td>\n73.7.6 Priority Resolution function
73.10 State diagrams and variable definitions
73.10.1 State diagram variables <\/td>\n<\/tr>\n
87<\/td>\n73.11 Protocol implementation conformance statement (PICS) proforma for Clause 73, Auto-Negotiation for backplane and copper cable assembly
73.11.4 PICS proforma tables for Auto-Negotiation for backplane and copper cable assembly
73.11.4.3 Link codeword encoding <\/td>\n<\/tr>\n
88<\/td>\n73.11.4.4 Receive function requirements <\/td>\n<\/tr>\n
89<\/td>\n74. Forward Error Correction (FEC) sublayer for BASE-R PHYs
74.5 FEC service interface
74.5.2 40GBASE-R and 100GBASE-R service primitives
74.7 FEC principle of operation
74.7.4 Functions within FEC sublayer <\/td>\n<\/tr>\n
90<\/td>\n74.7.4.8 FEC rapid block synchronization for EEE (optional) <\/td>\n<\/tr>\n
91<\/td>\n78. Energy-Efficient Ethernet (EEE)
78.1 Overview
78.1.1 LPI Signaling <\/td>\n<\/tr>\n
92<\/td>\n78.1.1.1 Interlayer Reconciliation sublayer service interfaces
78.1.2 LPI Client service interface
78.1.2.2 LP_IDLE.indication
78.1.2.2.3 When generated
78.1.3 Reconciliation sublayer operation
78.1.3.3 PHY LPI operation
78.1.3.3.1 PHY LPI transmit operation <\/td>\n<\/tr>\n
93<\/td>\n78.1.3.3.2 PHY LPI receive operation
78.1.4 PHY types optionally supporting EEE Supported PHY types <\/td>\n<\/tr>\n
94<\/td>\n78.2 LPI mode timing parameters description
78.3 Capabilities Negotiation <\/td>\n<\/tr>\n
95<\/td>\n78.4 Data Link Layer Capabilities
78.4.2 Control state diagrams
78.4.2.3 Variables <\/td>\n<\/tr>\n
97<\/td>\n78.4.2.4 Functions <\/td>\n<\/tr>\n
98<\/td>\n78.4.2.5 State diagrams <\/td>\n<\/tr>\n
99<\/td>\n78.4.3 State change procedure across a link <\/td>\n<\/tr>\n
100<\/td>\n78.4.3.1 Transmitting link partner\u2019s state change procedure across a link
78.4.3.2 Receiving link partner\u2019s state change procedure across a link <\/td>\n<\/tr>\n
101<\/td>\n78.5 Communication link access latency <\/td>\n<\/tr>\n
102<\/td>\n78.5.2 40 Gb\/s and 100 Gb\/s PHY extension using XLAUI or CAUI <\/td>\n<\/tr>\n
103<\/td>\n79. IEEE 802.3 Organizationally Specific Link Layer Discovery Protocol (LLDP) type, length, and value (TLV) information elements
79.3 IEEE 802.3 Organizationally Specific TLVs
79.3.6 EEE Fast Wake TLV
79.3.6.1 Transmit fast wake <\/td>\n<\/tr>\n
104<\/td>\n79.3.6.2 Receive fast wake
79.3.6.3 Echo of Transmit fast wake and Receive fast wake
79.3.6.4 EEE Fast Wake TLV usage rules
79.4 IEEE 802.3 Organizationally Specific TLV selection management
79.4.2 IEEE 802.3 Organizationally Specific TLV\/LLDP Local and Remote System group managed object class cross references <\/td>\n<\/tr>\n
105<\/td>\n79.5 Protocol implementation conformance statement (PICS) proforma for IEEE 802.3 Organizationally Specific Link Layer Discovery Protocol (LLDP) type, length, and values (TLV) information elements
79.5.3 Major capabilities\/options <\/td>\n<\/tr>\n
106<\/td>\n79.5.6a EEE Fast Wake TLV <\/td>\n<\/tr>\n
107<\/td>\n80. Introduction to 40 Gb\/s and 100 Gb\/s networks
80.1 Overview
80.1.1 Scope
80.1.2 Objectives
80.1.3 Relationship of 40 Gigabit and 100 Gigabit Ethernet to the ISO OSI reference model <\/td>\n<\/tr>\n
108<\/td>\n80.1.4 Nomenclature <\/td>\n<\/tr>\n
109<\/td>\n80.1.5 Physical Layer signaling systems <\/td>\n<\/tr>\n
111<\/td>\n80.2 Summary of 40 Gigabit and 100 Gigabit Ethernet sublayers
80.2.2 Physical Coding Sublayer (PCS)
80.2.3 Forward Error Correction (FEC) sublayers
80.2.4 Physical Medium Attachment (PMA) sublayer
80.2.5 Physical Medium Dependent (PMD) sublayer
80.2.6 Auto-Negotiation <\/td>\n<\/tr>\n
112<\/td>\n80.3 Service interface specification method and notation
80.3.1 Inter-sublayer service interface
80.3.2 Instances of the Inter-sublayer service interface <\/td>\n<\/tr>\n
115<\/td>\n80.3.3 Semantics of inter-sublayer service interface primitives
80.3.3.4 IS_TX_MODE.request
80.3.3.4.1 Semantics of the service primitive
80.3.3.4.2 When generated
80.3.3.4.3 Effect of receipt
80.3.3.5 IS_RX_MODE.request
80.3.3.5.1 Semantics of the service primitive
80.3.3.5.2 When generated
80.3.3.5.3 Effect of receipt
80.3.3.6 IS_RX_LPI_ACTIVE.request <\/td>\n<\/tr>\n
116<\/td>\n80.3.3.6.1 Semantics of the service primitive
80.3.3.6.2 When generated
80.3.3.6.3 Effect of receipt
80.3.3.7 IS_ENERGY_DETECT.indication
80.3.3.7.1 Semantics of the service primitive
80.3.3.7.2 When generated
80.3.3.7.3 Effect of receipt
80.3.3.8 IS_RX_TX_MODE.indication
80.3.3.8.1 Semantics of the service primitive <\/td>\n<\/tr>\n
117<\/td>\n80.3.3.8.2 When generated
80.3.3.8.3 Effect of receipt
80.4 Delay constraints
80.5 Skew constraints <\/td>\n<\/tr>\n
121<\/td>\n80.7 Protocol implementation conformance statement (PICS) proforma <\/td>\n<\/tr>\n
122<\/td>\n81. Reconciliation Sublayer (RS) and Media Independent Interface for 40 Gb\/s and 100 Gb\/s operation (XLGMII and CGMII)
81.1 Overview
81.1.1 Summary of major concepts
81.1.7 Mapping of XLGMII\/CGMII signals to PLS service primitives
81.1.7.3 Mapping of PLS_CARRIER.indication <\/td>\n<\/tr>\n
123<\/td>\n81.3 XLGMII\/CGMII functional specifications
81.3.1 Transmit
81.3.1.2 TXC (transmit control)
81.3.1.5 Transmit direction LPI transition <\/td>\n<\/tr>\n
124<\/td>\n81.3.2 Receive
81.3.2.2 RXC (receive control)
81.3.2.4 Receive direction LPI transition
81.3.4 Link fault signaling <\/td>\n<\/tr>\n
125<\/td>\n81.3a LPI Assertion and Detection <\/td>\n<\/tr>\n
126<\/td>\n81.3a.1 LPI messages
81.3a.2 Transmit LPI state diagram
81.3a.2.1 Variables and counters <\/td>\n<\/tr>\n
127<\/td>\n81.3a.2.2 State diagram
81.3a.3 Considerations for transmit system behavior
81.3a.4 Considerations for receive system behavior <\/td>\n<\/tr>\n
128<\/td>\n81.4 Protocol implementation conformance statement (PICS) proforma for Clause 81, Reconciliation Sublayer (RS) and Media Independent Interface for 40 Gb\/s and 100 Gb\/s operation
81.4.2 Identification
81.4.2.3 Major capabilities\/options
81.4.3 PICS proforma tables for Reconciliation Sublayer and Media Independent Interface for 40 Gb\/s and 100 Gb\/s operation
81.4.3.6 LPI functions <\/td>\n<\/tr>\n
129<\/td>\n82. Physical Coding Sublayer (PCS) for 64B\/66B, type 40GBASE-R and 100GBASE-R
82.1 Overview
82.1.3 Summary of 40GBASE-R and 100GBASE-R sublayers
82.1.4 Inter-sublayer interfaces
82.1.4.2 Physical Medium Attachment (PMA) or Forward Error Correction (FEC) service interface <\/td>\n<\/tr>\n
130<\/td>\n82.1.5 Functional block diagram <\/td>\n<\/tr>\n
131<\/td>\n82.2 Physical Coding Sublayer (PCS)
82.2.3 64B\/66B transmission code
82.2.3.4 Control codes
82.2.3.6 Idle (\/I\/)
82.2.8 BIP calculations
82.2.8a Rapid alignment marker insertion <\/td>\n<\/tr>\n
133<\/td>\n82.2.11 Block synchronization <\/td>\n<\/tr>\n
134<\/td>\n82.2.12 PCS lane deskew
82.2.18 Detailed functions and state diagrams
82.2.18.2 State variables
82.2.18.2.2 Variables <\/td>\n<\/tr>\n
136<\/td>\n82.2.18.2.3 Functions <\/td>\n<\/tr>\n
137<\/td>\n82.2.18.2.4 Counters
82.2.18.2.5 Timers <\/td>\n<\/tr>\n
138<\/td>\n82.2.18.3 State diagrams
82.2.18.3.1 LPI state diagrams <\/td>\n<\/tr>\n
139<\/td>\n82.3 PCS Management
82.3.1 PMD MDIO function mapping <\/td>\n<\/tr>\n
140<\/td>\n82.6 Auto-Negotiation <\/td>\n<\/tr>\n
149<\/td>\n82.7 Protocol implementation conformance statement (PICS) proforma for Clause 82, Physical Coding Sublayer (PCS) for 64B\/66B, type 40GBASE-R and 100GBASE-R
82.7.3 Major capabilities\/options
82.7.6.5 Auto-Negotiation for Backplane Ethernet functions <\/td>\n<\/tr>\n
150<\/td>\n82.7.6.6 LPI functions <\/td>\n<\/tr>\n
151<\/td>\n83. Physical Medium Attachment (PMA) sublayer, type 40GBASE-R and 100GBASE-R
83.1 Overview
83.1.1 Scope
83.3 PMA service interface <\/td>\n<\/tr>\n
152<\/td>\n83.5 Functions within the PMA
83.5.3 Skew and Skew Variation
83.5.3.a Skew generation toward SP0
83.5.3.7 Skew generation toward SP7
83.5.8 PMA local loopback mode <\/td>\n<\/tr>\n
153<\/td>\n83.5.11 Energy Efficient Ethernet
83.5.11.1 PMA quiet and alert signals <\/td>\n<\/tr>\n
154<\/td>\n83.5.11.2 Detection of PMA quiet and alert signals
83.5.11.3 Additional transmit functions in the Tx direction <\/td>\n<\/tr>\n
155<\/td>\n83.5.11.4 Additional receive functions in the Tx direction
83.5.11.5 Additional transmit functions in the Rx direction <\/td>\n<\/tr>\n
156<\/td>\n83.5.11.6 Additional receive functions in the Rx direction
83.5.11.7 Support for BASE-R FEC
83.6 PMA MDIO function mapping <\/td>\n<\/tr>\n
157<\/td>\n83.7 Protocol implementation conformance statement (PICS) proforma for Clause 83, Physical Medium Attachment (PMA) sublayer, type 40GBASE-R and 100GBASE-R
83.7.3 Major capabilities\/options
83.7.7 EEE deep sleep with XLAUI\/CAUI <\/td>\n<\/tr>\n
158<\/td>\n84. Physical Medium Dependent sublayer and baseband medium, type 40GBASE-KR4
84.1 Overview
84.2 Physical Medium Dependent (PMD) service interface
84.3 PCS requirements for Auto-Negotiation (AN) service interface <\/td>\n<\/tr>\n
159<\/td>\n84.6 PMD MDIO function mapping
84.7 PMD functional specifications
84.7.2 PMD Transmit function
84.7.4 Global PMD signal detect function <\/td>\n<\/tr>\n
160<\/td>\n84.7.6 Global PMD transmit disable function <\/td>\n<\/tr>\n
161<\/td>\n84.11 Protocol implementation conformance statement (PICS) proforma for Clause 84, Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-KR4
84.11.3 Major capabilities\/options
84.11.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10
84.11.4.1 PMD functional specifications
84.11.4.3 Transmitter electrical characteristics <\/td>\n<\/tr>\n
162<\/td>\n85. Physical Medium Dependent sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10
85.1 Overview
85.2 Physical Medium Dependent (PMD) service interface
85.3 PCS requirements for Auto-Negotiation (AN) service interface <\/td>\n<\/tr>\n
163<\/td>\n85.6 PMD MDIO function mapping
85.7 PMD functional specifications
85.7.2 PMD Transmit function
85.7.4 Global PMD signal detect function <\/td>\n<\/tr>\n
164<\/td>\n85.7.6 Global PMD transmit disable function
85.8.3 Transmitter characteristics
85.13 Protocol implementation conformance statement (PICS) proforma for Clause 85, Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10
85.13.3 Major capabilities\/options <\/td>\n<\/tr>\n
165<\/td>\n85.13.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10
85.13.4.1 PMD functional specifications
85.13.4.3 Transmitter specifications <\/td>\n<\/tr>\n
166<\/td>\n91. Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs
91.1 Overview
91.1.1 Scope
91.1.2 Position of RS-FEC in the 100GBASE-R sublayers
91.2 FEC service interface <\/td>\n<\/tr>\n
167<\/td>\n91.3 PMA compatibility <\/td>\n<\/tr>\n
168<\/td>\n91.4 Delay constraints
91.5 Functions within the RS-FEC sublayer
91.5.1 Functional block diagram
91.5.2 Transmit function
91.5.2.1 Lane block synchronization
91.5.2.2 Alignment lock and deskew
91.5.2.3 Lane reorder
91.5.2.4 Alignment marker removal <\/td>\n<\/tr>\n
170<\/td>\n91.5.2.5 64B\/66B to 256B\/257B transcoder <\/td>\n<\/tr>\n
171<\/td>\n91.5.2.6 Alignment marker mapping and insertion <\/td>\n<\/tr>\n
173<\/td>\n91.5.2.7 Reed-Solomon encoder <\/td>\n<\/tr>\n
175<\/td>\n91.5.2.8 Symbol distribution
91.5.2.9 Transmit bit ordering
91.5.3 Receive function
91.5.3.1 Alignment lock and deskew <\/td>\n<\/tr>\n
177<\/td>\n91.5.3.2 Lane reorder
91.5.3.3 Reed-Solomon decoder <\/td>\n<\/tr>\n
178<\/td>\n91.5.3.4 Alignment marker removal
91.5.3.5 256B\/257B to 64B\/66B transcoder <\/td>\n<\/tr>\n
179<\/td>\n91.5.3.6 Block distribution
91.5.3.7 Alignment marker mapping and insertion <\/td>\n<\/tr>\n
180<\/td>\n91.5.3.8 Receive bit ordering
91.5.4 Detailed functions and state diagrams
91.5.4.1 State diagram conventions <\/td>\n<\/tr>\n
182<\/td>\n91.5.4.2 State variables
91.5.4.2.1 Variables <\/td>\n<\/tr>\n
184<\/td>\n91.5.4.2.2 Functions
91.5.4.2.3 Counters <\/td>\n<\/tr>\n
185<\/td>\n91.5.4.3 State diagrams <\/td>\n<\/tr>\n
189<\/td>\n91.6 RS-FEC MDIO function mapping <\/td>\n<\/tr>\n
191<\/td>\n91.6.1 FEC_bypass_correction_enable
91.6.2 FEC_bypass_indication_enable
91.6.3 FEC_bypass_correction_ability
91.6.4 FEC_bypass_indication_ability
91.6.5 hi_ser
91.6.6 amps_lock
91.6.7 fec_align_status
91.6.8 FEC_corrected_cw_counter <\/td>\n<\/tr>\n
192<\/td>\n91.6.9 FEC_uncorrected_cw_counter
91.6.10 FEC_lane_mapping
91.6.11 FEC_symbol_error_counter_i
91.6.12 align_status
91.6.13 BIP_error_counter_i
91.6.14 lane_mapping
91.6.15 block_lock
91.6.16 am_lock <\/td>\n<\/tr>\n
193<\/td>\n91.7 Protocol implementation conformance statement (PICS) proforma for Clause 91, Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs
91.7.1 Introduction
91.7.2 Identification
91.7.2.1 Implementation identification
91.7.2.2 Protocol summary <\/td>\n<\/tr>\n
194<\/td>\n91.7.3 Major capabilities\/options
91.7.4 PICS proforma tables for Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs
91.7.4.1 Transmit function <\/td>\n<\/tr>\n
195<\/td>\n91.7.4.2 Receive function <\/td>\n<\/tr>\n
196<\/td>\n91.7.4.3 State diagrams <\/td>\n<\/tr>\n
197<\/td>\n92. Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-CR4
92.1 Overview <\/td>\n<\/tr>\n
198<\/td>\n92.2 Physical Medium Dependent (PMD) service interface <\/td>\n<\/tr>\n
199<\/td>\n92.3 PCS requirements for Auto-Negotiation (AN) service interface
92.4 Delay constraints
92.5 Skew constraints <\/td>\n<\/tr>\n
200<\/td>\n92.6 PMD MDIO function mapping <\/td>\n<\/tr>\n
201<\/td>\n92.7 PMD functional specifications
92.7.1 Link block diagram <\/td>\n<\/tr>\n
203<\/td>\n92.7.2 PMD Transmit function
92.7.3 PMD Receive function
92.7.4 Global PMD signal detect function
92.7.5 PMD lane-by-lane signal detect function <\/td>\n<\/tr>\n
204<\/td>\n92.7.6 Global PMD transmit disable function
92.7.7 PMD lane-by-lane transmit disable function
92.7.8 Loopback mode
92.7.9 PMD fault function
92.7.10 PMD transmit fault function <\/td>\n<\/tr>\n
205<\/td>\n92.7.11 PMD receive fault function
92.7.12 PMD control function <\/td>\n<\/tr>\n
206<\/td>\n92.8 100GBASE-CR4 electrical characteristics
92.8.1 Signal levels
92.8.2 Signal paths
92.8.3 Transmitter characteristics <\/td>\n<\/tr>\n
207<\/td>\n92.8.3.1 Signal levels <\/td>\n<\/tr>\n
208<\/td>\n92.8.3.2 Transmitter differential output return loss
92.8.3.3 Common-mode to differential mode output return loss <\/td>\n<\/tr>\n
209<\/td>\n92.8.3.4 Common-mode to common-mode output return loss <\/td>\n<\/tr>\n
210<\/td>\n92.8.3.5 Transmitter output waveform <\/td>\n<\/tr>\n
211<\/td>\n92.8.3.5.1 Linear fit to the measured waveform
92.8.3.5.2 Steady-state voltage and linear fit pulse peak <\/td>\n<\/tr>\n
212<\/td>\n92.8.3.5.3 Coefficient initialization
92.8.3.5.4 Coefficient step size
92.8.3.5.5 Coefficient range
92.8.3.6 Insertion loss TP0 to TP2 or TP3 to TP5 <\/td>\n<\/tr>\n
213<\/td>\n92.8.3.7 Transmitter output noise and distortion
92.8.3.8 Transmitter output jitter <\/td>\n<\/tr>\n
214<\/td>\n92.8.3.8.1 Even-odd jitter
92.8.3.8.2 Effective bounded uncorrelated jitter and effective random jitter <\/td>\n<\/tr>\n
215<\/td>\n92.8.3.9 Signaling rate range
92.8.4 Receiver characteristics <\/td>\n<\/tr>\n
216<\/td>\n92.8.4.1 Receiver input amplitude tolerance
92.8.4.2 Receiver differential input return loss
92.8.4.3 Differential to common-mode input return loss
92.8.4.4 Receiver interference tolerance test <\/td>\n<\/tr>\n
217<\/td>\n92.8.4.4.1 Test setup
92.8.4.4.2 Test channel <\/td>\n<\/tr>\n
218<\/td>\n92.8.4.4.3 Test channel calibration
92.8.4.4.4 Pattern generator <\/td>\n<\/tr>\n
219<\/td>\n92.8.4.4.5 Test procedure
92.8.4.5 Receiver jitter tolerance
92.8.4.6 Signaling rate range
92.9 Channel characteristics
92.10 Cable assembly characteristics <\/td>\n<\/tr>\n
220<\/td>\n92.10.1 Characteristic impedance and reference impedance
92.10.2 Cable assembly insertion loss <\/td>\n<\/tr>\n
222<\/td>\n92.10.3 Cable assembly differential return loss
92.10.4 Differential to common-mode return loss <\/td>\n<\/tr>\n
223<\/td>\n92.10.5 Differential to common-mode conversion loss <\/td>\n<\/tr>\n
224<\/td>\n92.10.6 Common-mode to common-mode return loss
92.10.7 Cable assembly Channel Operating Margin
92.10.7.1 Channel signal path <\/td>\n<\/tr>\n
225<\/td>\n92.10.7.1.1 TP0 to TP1 and TP4 to TP5 signal paths
92.10.7.2 Channel crosstalk paths <\/td>\n<\/tr>\n
226<\/td>\n92.11 Test fixtures
92.11.1 TP2 or TP3 test fixture
92.11.1.1 Test fixture return loss
92.11.1.2 Test fixture insertion loss <\/td>\n<\/tr>\n
228<\/td>\n92.11.2 Cable assembly test fixture
92.11.3 Mated test fixtures
92.11.3.1 Mated test fixtures insertion loss <\/td>\n<\/tr>\n
229<\/td>\n92.11.3.2 Mated test fixtures return loss <\/td>\n<\/tr>\n
230<\/td>\n92.11.3.3 Mated test fixtures common-mode conversion insertion loss
92.11.3.4 Mated test fixtures common-mode return loss <\/td>\n<\/tr>\n
232<\/td>\n92.11.3.5 Mated test fixtures common-mode to differential mode return loss
92.11.3.6 Mated test fixtures integrated crosstalk noise <\/td>\n<\/tr>\n
233<\/td>\n92.11.3.6.1 Mated test fixture multiple disturber near-end crosstalk (MDNEXT) loss
92.11.3.6.2 Mated test fixture multiple disturber far-end crosstalk (MDFEXT) loss
92.11.3.6.3 Mated test fixture integrated crosstalk noise (ICN) <\/td>\n<\/tr>\n
234<\/td>\n92.12 MDI specification <\/td>\n<\/tr>\n
235<\/td>\n92.12.1 100GBASE-CR4 MDI connectors
92.12.1.1 Style-1 100GBASE-CR4 MDI connectors <\/td>\n<\/tr>\n
236<\/td>\n92.12.1.2 Style-2 100GBASE-CR4 MDI connectors <\/td>\n<\/tr>\n
237<\/td>\n92.13 Environmental specifications <\/td>\n<\/tr>\n
238<\/td>\n92.14 Protocol implementation conformance statement (PICS) proforma for Clause 92, Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-CR4
92.14.1 Introduction
92.14.2 Identification
92.14.2.1 Implementation identification
92.14.2.2 Protocol summary <\/td>\n<\/tr>\n
239<\/td>\n92.14.3 Major capabilities\/options <\/td>\n<\/tr>\n
240<\/td>\n92.14.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-CR4
92.14.4.1 PMD functional specifications <\/td>\n<\/tr>\n
241<\/td>\n92.14.4.2 Management functions <\/td>\n<\/tr>\n
242<\/td>\n92.14.4.3 Transmitter specifications <\/td>\n<\/tr>\n
243<\/td>\n92.14.4.4 Receiver specifications <\/td>\n<\/tr>\n
244<\/td>\n92.14.4.5 Cable assembly specifications <\/td>\n<\/tr>\n
245<\/td>\n92.14.4.6 MDI connector specifications
92.14.4.7 Environmental specifications <\/td>\n<\/tr>\n
246<\/td>\n93. Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KR4
93.1 Overview <\/td>\n<\/tr>\n
247<\/td>\n93.2 Physical Medium Dependent (PMD) service interface <\/td>\n<\/tr>\n
248<\/td>\n93.3 PCS requirements for Auto-Negotiation (AN) service interface
93.4 Delay constraints
93.5 Skew constraints <\/td>\n<\/tr>\n
249<\/td>\n93.6 PMD MDIO function mapping <\/td>\n<\/tr>\n
250<\/td>\n93.7 PMD functional specifications
93.7.1 Link block diagram <\/td>\n<\/tr>\n
251<\/td>\n93.7.2 PMD Transmit function
93.7.3 PMD Receive function
93.7.4 Global PMD signal detect function
93.7.5 PMD lane-by-lane signal detect function <\/td>\n<\/tr>\n
252<\/td>\n93.7.6 Global PMD transmit disable function
93.7.7 PMD lane-by-lane transmit disable function
93.7.8 Loopback mode
93.7.9 PMD fault function
93.7.10 PMD transmit fault function <\/td>\n<\/tr>\n
253<\/td>\n93.7.11 PMD receive fault function
93.7.12 PMD control function <\/td>\n<\/tr>\n
254<\/td>\n93.8 100GBASE-KR4 electrical characteristics
93.8.1 Transmitter characteristics
93.8.1.1 Transmitter test fixture <\/td>\n<\/tr>\n
256<\/td>\n93.8.1.2 Signaling rate and range
93.8.1.3 Signal levels <\/td>\n<\/tr>\n
257<\/td>\n93.8.1.4 Transmitter output return loss
93.8.1.5 Transmitter output waveform <\/td>\n<\/tr>\n
259<\/td>\n93.8.1.5.1 Linear fit to the measured waveform
93.8.1.5.2 Steady-state voltage and linear fit pulse peak
93.8.1.5.3 Coefficient initialization
93.8.1.5.4 Coefficient step size
93.8.1.5.5 Coefficient range <\/td>\n<\/tr>\n
260<\/td>\n93.8.1.6 Transmitter output noise and distortion
93.8.1.7 Transmitter output jitter
93.8.2 Receiver characteristics
93.8.2.1 Receiver test fixture <\/td>\n<\/tr>\n
261<\/td>\n93.8.2.2 Receiver input return loss
93.8.2.3 Receiver interference tolerance <\/td>\n<\/tr>\n
262<\/td>\n93.8.2.4 Receiver jitter tolerance <\/td>\n<\/tr>\n
264<\/td>\n93.9 Channel characteristics
93.9.1 Channel Operating Margin
93.9.2 Insertion loss
93.9.3 Return loss <\/td>\n<\/tr>\n
266<\/td>\n93.9.4 AC-coupling
93.10 Environmental specifications
93.10.1 General safety <\/td>\n<\/tr>\n
267<\/td>\n93.10.2 Network safety
93.10.3 Installation and maintenance guidelines
93.10.4 Electromagnetic compatibility
93.10.5 Temperature and humidity <\/td>\n<\/tr>\n
268<\/td>\n93.11 Protocol implementation conformance statement (PICS) proforma for Clause 93, Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KR4
93.11.1 Introduction
93.11.2 Identification
93.11.2.1 Implementation identification
93.11.2.2 Protocol summary <\/td>\n<\/tr>\n
269<\/td>\n93.11.3 Major capabilities\/options <\/td>\n<\/tr>\n
270<\/td>\n93.11.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KR4
93.11.4.1 Functional specifications <\/td>\n<\/tr>\n
271<\/td>\n93.11.4.2 Transmitter characteristics <\/td>\n<\/tr>\n
273<\/td>\n93.11.4.3 Receiver characteristics <\/td>\n<\/tr>\n
274<\/td>\n93.11.4.4 Channel characteristics
93.11.4.5 Environmental specifications <\/td>\n<\/tr>\n
275<\/td>\n94. Physical Medium Attachment (PMA) sublayer, Physical Medium Dependent (PMD) sublayer, and baseband medium, type 100GBASE-KP4
94.1 Overview <\/td>\n<\/tr>\n
276<\/td>\n94.2 Physical Medium Attachment (PMA) Sublayer
94.2.1 PMA Service Interface <\/td>\n<\/tr>\n
277<\/td>\n94.2.1.1 PMA:IS_UNITDATA_i.request
94.2.1.1.1 Semantics of the service primitive
94.2.1.1.2 When generated
94.2.1.1.3 Effect of receipt
94.2.1.2 PMA:IS_UNITDATA_i.indication
94.2.1.2.1 Semantics of the service primitive <\/td>\n<\/tr>\n
278<\/td>\n94.2.1.2.2 When generated
94.2.1.2.3 Effect of receipt
94.2.1.3 PMA:IS_SIGNAL.indication
94.2.1.3.1 Semantics of the service primitive
94.2.1.3.2 When generated
94.2.1.3.3 Effect of receipt
94.2.1.4 PMA:IS_TX_MODE.request
94.2.1.4.1 Semantics of the service primitive
94.2.1.4.2 When generated
94.2.1.4.3 Effect of receipt <\/td>\n<\/tr>\n
279<\/td>\n94.2.1.5 PMA:IS_RX_MODE.request
94.2.1.5.1 Semantics of the service primitive
94.2.1.5.2 When generated
94.2.1.5.3 Effect of receipt
94.2.1.6 PMA:IS_ENERGY_DETECT.indication
94.2.1.6.1 Semantics of the service primitive
94.2.1.6.2 When generated
94.2.1.6.3 Effect of receipt
94.2.1.7 PMA:IS_RX_TX_MODE.indication <\/td>\n<\/tr>\n
280<\/td>\n94.2.1.7.1 Semantics of the service primitive
94.2.1.7.2 When generated
94.2.1.7.3 Effect of receipt
94.2.2 PMA Transmit Functional Specifications <\/td>\n<\/tr>\n
281<\/td>\n94.2.2.1 FEC Interface
94.2.2.2 Overhead Frame
94.2.2.3 Overhead <\/td>\n<\/tr>\n
282<\/td>\n94.2.2.4 Termination Blocks <\/td>\n<\/tr>\n
283<\/td>\n94.2.2.5 Gray Mapping
94.2.2.6 Precoding
94.2.2.7 PAM4 encoding <\/td>\n<\/tr>\n
284<\/td>\n94.2.2.8 PMD Interface
94.2.3 PMA Receive Functional Specifications <\/td>\n<\/tr>\n
285<\/td>\n94.2.3.1 Overhead
94.2.4 Skew constraints
94.2.5 Delay constraints
94.2.6 Link status
94.2.7 PMA local loopback mode <\/td>\n<\/tr>\n
286<\/td>\n94.2.8 PMA remote loopback mode (optional)
94.2.9 PMA test patterns
94.2.9.1 JP03A test pattern
94.2.9.2 JP03B test pattern
94.2.9.3 Quaternary PRBS13 test pattern <\/td>\n<\/tr>\n
287<\/td>\n94.2.9.4 Transmitter linearity test pattern
94.2.10 PMA MDIO function mapping <\/td>\n<\/tr>\n
288<\/td>\n94.3 Physical Medium Dependent (PMD) Sublayer
94.3.1 Physical Medium Dependent (PMD) service interface <\/td>\n<\/tr>\n
289<\/td>\n94.3.1.1 PMD:IS_UNITDATA_i.request
94.3.1.1.1 Semantics of the service primitive
94.3.1.1.2 When generated
94.3.1.1.3 Effect of receipt
94.3.1.2 PMD:IS_UNITDATA_i.indication
94.3.1.2.1 Semantics of the service primitive
94.3.1.2.2 When generated
94.3.1.2.3 Effect of receipt <\/td>\n<\/tr>\n
290<\/td>\n94.3.1.3 PMD:IS_SIGNAL.indication
94.3.1.3.1 Semantics of the service primitive
94.3.1.3.2 When generated
94.3.1.3.3 Effect of receipt
94.3.2 PCS requirements for Auto-Negotiation (AN) service interface
94.3.3 Delay constraints
94.3.4 Skew constraints <\/td>\n<\/tr>\n
291<\/td>\n94.3.5 PMD MDIO function mapping <\/td>\n<\/tr>\n
292<\/td>\n94.3.6 PMD functional specifications
94.3.6.1 Link block diagram <\/td>\n<\/tr>\n
293<\/td>\n94.3.6.2 PMD Transmit function
94.3.6.3 PMD Receive function
94.3.6.4 Global PMD signal detect function
94.3.6.5 PMD lane-by-lane signal detect function
94.3.6.6 Global PMD transmit disable function <\/td>\n<\/tr>\n
294<\/td>\n94.3.6.7 PMD lane-by-lane transmit disable function
94.3.6.8 Loopback mode
94.3.7 PMD fault function
94.3.8 PMD transmit fault function <\/td>\n<\/tr>\n
295<\/td>\n94.3.9 PMD receive fault function
94.3.10 PMD control function
94.3.10.1 Overview
94.3.10.2 Training frame structure <\/td>\n<\/tr>\n
296<\/td>\n94.3.10.3 Training frame words
94.3.10.4 Frame marker
94.3.10.5 Control channel encoding
94.3.10.5.1 Differential Manchester encoding
94.3.10.5.2 Control channel structure
94.3.10.6 Coefficient update field <\/td>\n<\/tr>\n
298<\/td>\n94.3.10.6.1 Preset
94.3.10.6.2 Initialize
94.3.10.6.3 Parity
94.3.10.6.4 Coefficient (k) update
94.3.10.7 Status report field <\/td>\n<\/tr>\n
299<\/td>\n94.3.10.7.1 Parity
94.3.10.7.2 Training frame countdown
94.3.10.7.3 Receiver ready <\/td>\n<\/tr>\n
300<\/td>\n94.3.10.7.4 Coefficient (k) status
94.3.10.7.5 Coefficient update process
94.3.10.8 Training pattern <\/td>\n<\/tr>\n
301<\/td>\n94.3.10.9 Transition from training to data
94.3.10.10 Frame lock state diagram
94.3.10.11 Training state diagram <\/td>\n<\/tr>\n
303<\/td>\n94.3.10.12 Coefficient update state diagram
94.3.11 PMD LPI function
94.3.11.1 Alert Signal
94.3.11.1.1 Frame marker <\/td>\n<\/tr>\n
304<\/td>\n94.3.11.1.2 Coefficient update field
94.3.11.1.3 Status report field
94.3.11.1.4 Parity
94.3.11.1.5 Mode
94.3.11.1.6 Alert frame countdown
94.3.11.1.7 PMA alignment offset <\/td>\n<\/tr>\n
305<\/td>\n94.3.11.1.8 Receiver ready
94.3.11.1.9 Transition from alert to data
94.3.12 PMD Transmitter electrical characteristics <\/td>\n<\/tr>\n
306<\/td>\n94.3.12.1 Test fixture
94.3.12.1.1 Test fixture impedance <\/td>\n<\/tr>\n
308<\/td>\n94.3.12.1.2 Test fixture insertion loss
94.3.12.2 Signaling rate and range
94.3.12.3 Signal levels <\/td>\n<\/tr>\n
309<\/td>\n94.3.12.4 Transmitter output return loss <\/td>\n<\/tr>\n
310<\/td>\n94.3.12.5 Transmitter output waveform <\/td>\n<\/tr>\n
311<\/td>\n94.3.12.5.1 Transmitter linearity <\/td>\n<\/tr>\n
312<\/td>\n94.3.12.5.2 Linear fit to the measured waveform
94.3.12.5.3 Steady-state voltage and linear fit pulse peak
94.3.12.5.4 Coefficient initialization <\/td>\n<\/tr>\n
313<\/td>\n94.3.12.5.5 Coefficient step size
94.3.12.5.6 Coefficient range
94.3.12.6 Transmitter output jitter
94.3.12.6.1 Clock random jitter and clock deterministic jitter <\/td>\n<\/tr>\n
314<\/td>\n94.3.12.6.2 Even-odd jitter <\/td>\n<\/tr>\n
315<\/td>\n94.3.12.7 Transmitter output noise and distortion
94.3.13 PMD Receiver electrical characteristics
94.3.13.1 Test fixture <\/td>\n<\/tr>\n
316<\/td>\n94.3.13.2 Receiver input return loss
94.3.13.3 Receiver interference tolerance <\/td>\n<\/tr>\n
319<\/td>\n94.3.13.4 Receiver jitter tolerance
94.3.13.4.1 Test setup
94.3.13.4.2 Test method
94.4 Channel characteristics
94.4.1 Channel Operating Margin
94.4.2 Channel insertion loss <\/td>\n<\/tr>\n
321<\/td>\n94.4.3 Channel return loss <\/td>\n<\/tr>\n
322<\/td>\n94.4.4 Channel AC-coupling
94.5 Environmental specifications
94.5.1 General safety
94.5.2 Network safety <\/td>\n<\/tr>\n
323<\/td>\n94.5.3 Installation and maintenance guidelines
94.5.4 Electromagnetic compatibility
94.5.5 Temperature and humidity <\/td>\n<\/tr>\n
324<\/td>\n94.6 Protocol implementation conformance statement (PICS) proforma for Clause 94, Physical Medium Attachment (PMA) and Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KP4
94.6.1 Introduction
94.6.2 Identification
94.6.2.1 Implementation identification
94.6.2.2 Protocol summary <\/td>\n<\/tr>\n
325<\/td>\n94.6.3 Major capabilities\/options
94.6.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KP4
94.6.4.1 PMA functional specifications <\/td>\n<\/tr>\n
326<\/td>\n94.6.4.2 PMD functional specifications <\/td>\n<\/tr>\n
330<\/td>\n94.6.4.3 PMD transmitter characteristics <\/td>\n<\/tr>\n
331<\/td>\n94.6.4.4 PMD receiver characteristics <\/td>\n<\/tr>\n
332<\/td>\n94.6.4.5 Channel characteristics
94.6.4.6 Environment specifications <\/td>\n<\/tr>\n
333<\/td>\nAnnex 83A (normative) 40 Gb\/s Attachment Unit Interface (XLAUI) and 100 Gb\/s Attachment Unit Interface (CAUI)
83A.3 XLAUI\/CAUI electrical characteristics
83A.3.2a EEE operation
83A.3.3 Transmitter characteristics
83A.3.3.1 Output amplitude
83A.3.3.1.1 Amplitude and swing
83A.3.3.6 Global transmit disable function <\/td>\n<\/tr>\n
334<\/td>\n83A.3.4 Receiver characteristics
83A.3.4.7 Global energy detect function
83A.7 Protocol implementation conformance statement (PICS) proforma for Annex 83A, 40 Gb\/s Attachment Unit Interface (XLAUI) and 100 Gb\/s Attachment Unit Interface (CAUI)
83A.7.3 Major capabilities\/options
83A.7.4 XLAUI\/CAUI transmitter requirements <\/td>\n<\/tr>\n
335<\/td>\n83A.7.5 XLAUI\/CAUI receiver requirements <\/td>\n<\/tr>\n
336<\/td>\nAnnex 83C (informative) PMA sublayer partitioning examples
83C.1 Partitioning examples with FEC
83C.1.1 FEC implemented with PCS <\/td>\n<\/tr>\n
337<\/td>\n83C.1.2 FEC implemented with PMD <\/td>\n<\/tr>\n
338<\/td>\n83C.1a Partitioning examples with RS-FEC
83C.1a.1 Single PMA sublayer with RS-FEC <\/td>\n<\/tr>\n
339<\/td>\n83C.1a.2 Single CAUI with RS-FEC <\/td>\n<\/tr>\n
340<\/td>\nAnnex 91A (informative) RS-FEC codeword examples
91A.1 Input to the 64B\/66B to 256B\/257B transcoder <\/td>\n<\/tr>\n
341<\/td>\n91A.2 Output of the RS(528,514) encoder <\/td>\n<\/tr>\n
342<\/td>\n91A.3 Output of the RS(544,514) encoder
91A.4 Reed-Solomon encoder model <\/td>\n<\/tr>\n
343<\/td>\n91A.4.1 Global variable declarations for RS(528,514)
91A.4.2 Global variable declarations for RS(544,514)
91A.4.3 Other global variable declarations
91A.4.4 GF(210) multiplier function
91A.4.5 Reed-Solomon encoder function <\/td>\n<\/tr>\n
344<\/td>\n91A.4.6 Main function <\/td>\n<\/tr>\n
345<\/td>\nAnnex 92A (informative) 100GBASE-CR4 TP0 and TP5 test point parameters and channel characteristics
92A.1 Overview
92A.2 Transmitter characteristics at TP0
92A.3 Receiver characteristics at TP5
92A.4 Transmitter and receiver differential printed circuit board trace loss <\/td>\n<\/tr>\n
346<\/td>\n92A.5 Channel insertion loss <\/td>\n<\/tr>\n
348<\/td>\n92A.6 Channel return loss
92A.7 Channel Operating Margin (COM) <\/td>\n<\/tr>\n
349<\/td>\nAnnex 93A (normative) Specification methods for electrical channels
93A.1 Channel Operating Margin <\/td>\n<\/tr>\n
351<\/td>\n93A.1.1 Measurement of the channel
93A.1.2 Transmitter and receiver device package models <\/td>\n<\/tr>\n
352<\/td>\n93A.1.2.1 Cascade connection of two-port networks
93A.1.2.2 Two-port network for a shunt capacitance
93A.1.2.3 Two-port network for the package transmission line <\/td>\n<\/tr>\n
353<\/td>\n93A.1.2.4 Assembly of transmitter and receiver device package models
93A.1.3 Path terminations <\/td>\n<\/tr>\n
354<\/td>\n93A.1.4 Filters
93A.1.4.1 Receiver noise filter
93A.1.4.2 Transmitter equalizer
93A.1.4.3 Receiver equalizer <\/td>\n<\/tr>\n
355<\/td>\n93A.1.5 Pulse response
93A.1.6 Determination of variable equalizer parameters <\/td>\n<\/tr>\n
357<\/td>\n93A.1.7 Interference and noise amplitude
93A.1.7.1 Interference amplitude distribution
93A.1.7.2 Noise amplitude distribution <\/td>\n<\/tr>\n
358<\/td>\n93A.1.7.3 Combination of interference and noise distributions <\/td>\n<\/tr>\n
359<\/td>\n93A.2 Test channel calibration using COM <\/td>\n<\/tr>\n
360<\/td>\n93A.3 Fitted insertion loss <\/td>\n<\/tr>\n
361<\/td>\n93A.4 Insertion loss deviation <\/td>\n<\/tr>\n
362<\/td>\nAnnex 93B (informative) Electrical backplane reference model <\/td>\n<\/tr>\n
363<\/td>\nAnnex 93C (normative) Receiver interference tolerance
93C.1 Test setup <\/td>\n<\/tr>\n
366<\/td>\n93C.2 Test method <\/td>\n<\/tr>\n
368<\/td>\nBack cover <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Ethernet Amendment 2: Physical Layer Specifications and Management Parameters for 100 Gb\/s Operation Over Backplanes and Copper Cables<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2014<\/td>\n368<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":398059,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-398052","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/398052","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/398059"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=398052"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=398052"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=398052"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}