{"id":257863,"date":"2024-10-19T17:03:42","date_gmt":"2024-10-19T17:03:42","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-iso-17458-22013\/"},"modified":"2024-10-25T12:38:58","modified_gmt":"2024-10-25T12:38:58","slug":"bs-iso-17458-22013","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-iso-17458-22013\/","title":{"rendered":"BS ISO 17458-2:2013"},"content":{"rendered":"

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
11<\/td>\n1 Scope
2 Normative references
3 Terms, definitions, symbols and abbreviated terms
3.1 Terms and definitions <\/td>\n<\/tr>\n
17<\/td>\n3.2 Symbols
3.3 Abbreviated terms <\/td>\n<\/tr>\n
20<\/td>\n4 Document overview <\/td>\n<\/tr>\n
21<\/td>\n5 Conventions
5.1 General
5.2 Notational conventions
5.2.1 Parameter prefix conventions <\/td>\n<\/tr>\n
22<\/td>\n5.2.2 Text coding
5.2.3 Implementation dependent behaviour
5.3 SDL conventions
5.3.1 General <\/td>\n<\/tr>\n
23<\/td>\n5.3.2 SDL notational conventions
5.3.3 SDL extensions
5.3.3.1 General
5.3.3.2 Microtick, macrotick and sample tick timers <\/td>\n<\/tr>\n
24<\/td>\n5.3.3.3 Microtick behaviour of the ‘now’ \u2013 expression
5.3.3.4 Channel-specific process replication
5.3.3.5 Handling of priority input symbols <\/td>\n<\/tr>\n
25<\/td>\n5.3.3.6 Signals to non-instantiated processes
5.3.3.7 Exported and imported signals
5.4 Bit rates
5.5 Roles of a node in a FlexRay cluster
5.6 Synchronisation methods
5.6.1 General <\/td>\n<\/tr>\n
26<\/td>\n5.6.2 TT-D synchronisation method
5.6.3 TT-L synchronisation method <\/td>\n<\/tr>\n
27<\/td>\n5.6.4 TT-E synchronisation method <\/td>\n<\/tr>\n
29<\/td>\n5.7 Network topology considerations
5.7.1 General <\/td>\n<\/tr>\n
30<\/td>\n5.7.2 Passive bus topology
5.7.3 Active star topology <\/td>\n<\/tr>\n
32<\/td>\n5.7.4 Active star topology combined with a passive bus top <\/td>\n<\/tr>\n
34<\/td>\n5.8 Example node architecture
5.8.1 Objective
5.8.2 Overview <\/td>\n<\/tr>\n
35<\/td>\n5.8.3 Host – communication controller interface
5.8.4 Communication controller – bus driver interface <\/td>\n<\/tr>\n
37<\/td>\n5.8.5 Bus driver – host interface
5.8.5.1 Overview
5.8.5.2 Hard wired signals (option A)
5.8.5.3 Serial peripheral interface (SPI) (option B) <\/td>\n<\/tr>\n
38<\/td>\n5.8.6 Bus driver – power supply interface (optional)
5.8.7 Time gateway interface <\/td>\n<\/tr>\n
39<\/td>\n5.8.8 Testability requirements
6 Protocol operation control
6.1 Principles
6.1.1 General <\/td>\n<\/tr>\n
40<\/td>\n6.1.2 Communication controller power moding <\/td>\n<\/tr>\n
41<\/td>\n6.2 Description
6.2.1 Protocol operation control context <\/td>\n<\/tr>\n
42<\/td>\n6.2.2 Operational overview
6.2.2.1 General
6.2.2.2 Host commands <\/td>\n<\/tr>\n
44<\/td>\n6.2.2.3 Error conditions
6.2.2.3.1 General
6.2.2.3.2 Errors causing immediate entry to the POC:halt state
6.2.2.3.3 Errors handled by the degradation model <\/td>\n<\/tr>\n
45<\/td>\n6.2.2.4 POC status <\/td>\n<\/tr>\n
46<\/td>\n6.2.2.5 SDL considerations for single channel nodes <\/td>\n<\/tr>\n
47<\/td>\n6.3 The protocol operation control process
6.3.1 General
6.3.2 POC SDL utilities <\/td>\n<\/tr>\n
49<\/td>\n6.3.3 SDL organization <\/td>\n<\/tr>\n
50<\/td>\n6.3.4 Preempting commands <\/td>\n<\/tr>\n
51<\/td>\n6.3.5 Deferred commands
6.3.5.1 DEFERRED_HALT, DEFERRED_READY and CLEAR_DEFERRED commands <\/td>\n<\/tr>\n
54<\/td>\n6.3.5.2 ALL_SLOTS command
6.3.6 Reaching the POC:ready state
6.3.6.1 State sequence to reach the POC:ready state <\/td>\n<\/tr>\n
56<\/td>\n6.3.6.2 Default configuration requirements <\/td>\n<\/tr>\n
57<\/td>\n6.3.7 Reaching the POC:normal active state
6.3.7.1 Host commands before reaching the POC:normal active state <\/td>\n<\/tr>\n
58<\/td>\n6.3.7.2 Wakeup and startup support <\/td>\n<\/tr>\n
60<\/td>\n6.3.8 Behaviour during normal operation
6.3.8.1 General
6.3.8.2 Cyclic behaviour
6.3.8.2.1 Recurring Tasks <\/td>\n<\/tr>\n
61<\/td>\n6.3.8.2.2 Cycle counter
6.3.8.2.3 POC:normal active state <\/td>\n<\/tr>\n
62<\/td>\n6.3.8.2.4 POC:normal passive state <\/td>\n<\/tr>\n
64<\/td>\n6.3.8.2.5 Error checking during normal operation
6.3.8.2.5.1 Error checking overview <\/td>\n<\/tr>\n
65<\/td>\n6.3.8.2.5.2 Error checking details for the POC:normal active state <\/td>\n<\/tr>\n
67<\/td>\n6.3.8.2.5.3 Error checking details for the POC:normal passive state <\/td>\n<\/tr>\n
69<\/td>\n7 Coding and Decoding
7.1 Principles
7.2 Description <\/td>\n<\/tr>\n
70<\/td>\n7.2.1 Frame and symbol encoding
7.2.1.1 General
7.2.1.2 Frame encoding
7.2.1.2.1 Transmission start sequence <\/td>\n<\/tr>\n
71<\/td>\n7.2.1.2.2 Frame start sequence
7.2.1.2.3 Byte start sequence
7.2.1.2.4 Frame end sequence
7.2.1.2.5 Dynamic trailing sequence <\/td>\n<\/tr>\n
72<\/td>\n7.2.1.2.6 Frame bit stream assembly <\/td>\n<\/tr>\n
73<\/td>\n7.2.1.3 Symbol encoding
7.2.1.3.1 General
7.2.1.3.2 Collision avoidance symbol and media access test symbol <\/td>\n<\/tr>\n
74<\/td>\n7.2.1.3.3 Wakeup symbol <\/td>\n<\/tr>\n
76<\/td>\n7.2.1.3.4 Wakeup During Operation Pattern (WUDOP) <\/td>\n<\/tr>\n
77<\/td>\n7.2.2 Sampling and majority voting <\/td>\n<\/tr>\n
78<\/td>\n7.2.3 Bit clock alignment and bit strobing <\/td>\n<\/tr>\n
80<\/td>\n7.2.4 Implementation specific delays
7.2.5 Channel idle detection
7.2.6 Action point and time reference point <\/td>\n<\/tr>\n
82<\/td>\n7.2.7 Frame and symbol decoding
7.2.7.1 Overview <\/td>\n<\/tr>\n
83<\/td>\n7.2.7.2 Frame decoding <\/td>\n<\/tr>\n
84<\/td>\n7.2.7.3 Symbol decoding
7.2.7.3.1 Collision avoidance symbol and media access test symbol decoding <\/td>\n<\/tr>\n
85<\/td>\n7.2.7.3.2 Wakeup symbol decoding <\/td>\n<\/tr>\n
86<\/td>\n7.2.7.4 Decoding error
7.2.8 Signal integrity <\/td>\n<\/tr>\n
87<\/td>\n7.3 Coding and decoding process
7.3.1 Operating modes
7.3.2 Coding and decoding process behaviour <\/td>\n<\/tr>\n
89<\/td>\n7.3.3 Encoding behaviour <\/td>\n<\/tr>\n
92<\/td>\n7.3.4 Encoding macros <\/td>\n<\/tr>\n
97<\/td>\n7.3.5 Decoding behaviour <\/td>\n<\/tr>\n
98<\/td>\n7.3.6 Decoding macros <\/td>\n<\/tr>\n
106<\/td>\n7.4 Bit strobing process
7.4.1 Operating modes <\/td>\n<\/tr>\n
107<\/td>\n7.4.2 Bit strobing process behaviour <\/td>\n<\/tr>\n
109<\/td>\n7.5 Wakeup pattern decoding process
7.5.1 Operating modes <\/td>\n<\/tr>\n
110<\/td>\n7.5.2 Wakeup pattern decoding process behaviour <\/td>\n<\/tr>\n
113<\/td>\n8 Frame Format
8.1 Overview
8.2 FlexRay header segment (5\u00a0bytes)
8.2.1 General <\/td>\n<\/tr>\n
114<\/td>\n8.2.2 Reserved bit (1\u00a0bit)
8.2.3 Payload preamble indicator (1\u00a0bit)
8.2.4 Null frame indicator (1\u00a0bit) <\/td>\n<\/tr>\n
115<\/td>\n8.2.5 Sync frame indicator (1\u00a0bit)
8.2.6 Startup frame indicator (1\u00a0bit) <\/td>\n<\/tr>\n
116<\/td>\n8.2.7 Frame ID (11\u00a0bits)
8.2.8 Payload length (7\u00a0bits) <\/td>\n<\/tr>\n
117<\/td>\n8.2.9 Header CRC (11\u00a0bits) <\/td>\n<\/tr>\n
118<\/td>\n8.2.10 Cycle count (6\u00a0bits)
8.2.11 Formal header definition
8.3 FlexRay payload segment (0\u00a0\u2013\u00a0254\u00a0bytes)
8.3.1 Payload <\/td>\n<\/tr>\n
119<\/td>\n8.3.2 NMVector <\/td>\n<\/tr>\n
120<\/td>\n8.3.3 Message ID (16\u00a0bits) <\/td>\n<\/tr>\n
121<\/td>\n8.4 FlexRay trailer segment
8.5 CRC calculation details
8.5.1 Context of the CRC calculation <\/td>\n<\/tr>\n
122<\/td>\n8.5.2 CRC calculation algorithm
8.5.3 Header CRC calculation <\/td>\n<\/tr>\n
123<\/td>\n8.5.4 Frame CRC calculation
9 Media Access Control
9.1 Principles
9.1.1 Overview
9.1.2 Communication cycle <\/td>\n<\/tr>\n
124<\/td>\n9.1.3 Communication cycle execution <\/td>\n<\/tr>\n
126<\/td>\n9.1.4 Static segment
9.1.4.1 Structure of the static segment
9.1.4.2 Execution and timing of the static segment <\/td>\n<\/tr>\n
127<\/td>\n9.1.5 Dynamic segment
9.1.5.1 Structure of the dynamic segment <\/td>\n<\/tr>\n
128<\/td>\n9.1.5.2 Execution and timing of the dynamic segment <\/td>\n<\/tr>\n
132<\/td>\n9.1.6 Symbol window
9.1.7 Network idle time <\/td>\n<\/tr>\n
133<\/td>\n9.2 Description
9.2.1 Relationship to other processes <\/td>\n<\/tr>\n
134<\/td>\n9.2.2 Operating modes
9.2.3 Significant events
9.2.3.1 Event types
9.2.3.2 Reception-related events <\/td>\n<\/tr>\n
136<\/td>\n9.2.3.3 Transmission-related events
9.2.3.4 Timing-related events
9.3 Media access control process
9.3.1 States of the media access control process <\/td>\n<\/tr>\n
138<\/td>\n9.3.2 Initialisation and MAC:standby state <\/td>\n<\/tr>\n
139<\/td>\n9.3.3 Static segment related states
9.3.3.1 State machine for the static segment media access control <\/td>\n<\/tr>\n
141<\/td>\n9.3.3.2 Transmission conditions and frame assembly in the static segment <\/td>\n<\/tr>\n
144<\/td>\n9.3.4 Dynamic segment related states
9.3.4.1 State machine for the dynamic segment media access control <\/td>\n<\/tr>\n
150<\/td>\n9.3.4.2 Transmission conditions and frame assembly in the dynamic segment <\/td>\n<\/tr>\n
151<\/td>\n9.3.5 Symbol window related states <\/td>\n<\/tr>\n
152<\/td>\n9.3.6 Network idle time <\/td>\n<\/tr>\n
153<\/td>\n10 Frame and Symbol processing
10.1 Principles
10.2 Description
10.2.1 Relationship to other processes <\/td>\n<\/tr>\n
154<\/td>\n10.2.2 Operating modes <\/td>\n<\/tr>\n
155<\/td>\n10.2.3 Significant events
10.2.3.1 General
10.2.3.2 Reception-related events <\/td>\n<\/tr>\n
156<\/td>\n10.2.3.3 Decoding-related events
10.2.3.4 Timing-related events <\/td>\n<\/tr>\n
157<\/td>\n10.2.4 Status data <\/td>\n<\/tr>\n
159<\/td>\n10.3 Frame and symbol processing process
10.3.1 States of the frame and symbol processing process <\/td>\n<\/tr>\n
160<\/td>\n10.3.2 Initialisation and FSP:standby state <\/td>\n<\/tr>\n
162<\/td>\n10.3.3 Macro SLOT_SEGMENT_END <\/td>\n<\/tr>\n
163<\/td>\n10.3.4 FSP:wait for CE start state <\/td>\n<\/tr>\n
164<\/td>\n10.3.5 FSP:decoding in progress state
10.3.5.1 Conditions to leave the FSP:decoding in progress state <\/td>\n<\/tr>\n
166<\/td>\n10.3.5.2 Frame reception checks during non-synchronized operation <\/td>\n<\/tr>\n
167<\/td>\n10.3.5.3 Frame reception checks during synchronized operation
10.3.5.3.1 Frame reception checks in the static segment <\/td>\n<\/tr>\n
168<\/td>\n10.3.5.3.2 Frame reception checks in the dynamic segment <\/td>\n<\/tr>\n
170<\/td>\n10.3.6 FSP:wait for CHIRP state <\/td>\n<\/tr>\n
171<\/td>\n10.3.7 FSP:wait for transmission end state
11 Wakeup and Startup
11.1 General <\/td>\n<\/tr>\n
172<\/td>\n11.2 Cluster wakeup
11.2.1 Principles
11.2.2 Description <\/td>\n<\/tr>\n
173<\/td>\n11.2.3 Wakeup support by the communication controller
11.2.3.1 Host interaction <\/td>\n<\/tr>\n
174<\/td>\n11.2.3.2 Wakeup state diagram <\/td>\n<\/tr>\n
175<\/td>\n11.2.3.3 The POC:wakeup listen state <\/td>\n<\/tr>\n
176<\/td>\n11.2.3.4 The POC:wakeup send state <\/td>\n<\/tr>\n
177<\/td>\n11.2.3.5 The POC:wakeup detect state
11.3 Communication startup and reintegration
11.3.1 General <\/td>\n<\/tr>\n
178<\/td>\n11.3.2 Principles
11.3.2.1 Definition and properties
11.3.2.2 Principle of operation
11.3.2.2.1 General
11.3.2.2.2 Startup performed by the coldstart nodes <\/td>\n<\/tr>\n
179<\/td>\n11.3.2.2.3 Integration of the non-coldstart nodes
11.3.3 Description <\/td>\n<\/tr>\n
180<\/td>\n11.3.4 Coldstart inhibit mode
11.3.5 Startup state diagram
11.3.5.1 Overview of the different startup paths <\/td>\n<\/tr>\n
183<\/td>\n11.3.5.2 Path of a TT-D leading coldstart node <\/td>\n<\/tr>\n
184<\/td>\n11.3.5.3 Path of a TT-D following coldstart node
11.3.5.4 Path of a TT-L coldstart node <\/td>\n<\/tr>\n
185<\/td>\n11.3.5.5 Path of a TT-E coldstart node <\/td>\n<\/tr>\n
188<\/td>\n11.3.5.6 Path of a non-coldstart node <\/td>\n<\/tr>\n
189<\/td>\n11.3.5.7 The POC:coldstart listen state <\/td>\n<\/tr>\n
191<\/td>\n11.3.5.8 The POC:coldstart collision resolution state <\/td>\n<\/tr>\n
192<\/td>\n11.3.5.9 The POC:coldstart consistency check state <\/td>\n<\/tr>\n
193<\/td>\n11.3.5.10 The POC:coldstart gap state <\/td>\n<\/tr>\n
194<\/td>\n11.3.5.11 The POC:initialize schedule state <\/td>\n<\/tr>\n
195<\/td>\n11.3.5.12 The POC:integration coldstart check state <\/td>\n<\/tr>\n
196<\/td>\n11.3.5.13 The POC:coldstart join state <\/td>\n<\/tr>\n
197<\/td>\n11.3.5.14 The POC:integration listen state <\/td>\n<\/tr>\n
198<\/td>\n11.3.5.15 The POC:integration consistency check state <\/td>\n<\/tr>\n
200<\/td>\n12 Clock synchronisation
12.1 Introduction <\/td>\n<\/tr>\n
201<\/td>\n12.2 Time representation
12.2.1 Timing hierarchy <\/td>\n<\/tr>\n
202<\/td>\n12.2.2 Global and local time
12.2.3 Parameters and variables <\/td>\n<\/tr>\n
203<\/td>\n12.3 Synchronisation process <\/td>\n<\/tr>\n
210<\/td>\n12.4 Startup of the clock synchronisation
12.4.1 Preconditions and startup types <\/td>\n<\/tr>\n
212<\/td>\n12.4.2 Coldstart startup
12.4.3 Integration startup <\/td>\n<\/tr>\n
214<\/td>\n12.5 Time measurement
12.5.1 General
12.5.2 Data structure <\/td>\n<\/tr>\n
215<\/td>\n12.5.3 Initialisation <\/td>\n<\/tr>\n
216<\/td>\n12.5.4 Time measurement storage <\/td>\n<\/tr>\n
218<\/td>\n12.6 Correction term calculation
12.6.1 Fault-tolerant midpoint algorithm <\/td>\n<\/tr>\n
219<\/td>\n12.6.2 Calculation of the offset correction value <\/td>\n<\/tr>\n
221<\/td>\n12.6.3 Calculation of the rate correction value <\/td>\n<\/tr>\n
223<\/td>\n12.6.4 Value limitations <\/td>\n<\/tr>\n
224<\/td>\n12.6.5 Host-controlled external clock synchronisation
12.6.6 TT-E time gateway sink correction determination <\/td>\n<\/tr>\n
230<\/td>\n12.7 Clock correction <\/td>\n<\/tr>\n
233<\/td>\n12.8 Sync frame configuration
12.8.1 Configuration rules <\/td>\n<\/tr>\n
234<\/td>\n12.8.2 TT-D cluster
12.8.3 TT-E cluster <\/td>\n<\/tr>\n
235<\/td>\n12.8.4 TT-L cluster
12.9 Time gateway interface <\/td>\n<\/tr>\n
236<\/td>\n13 Controller Host Interface
13.1 Principles <\/td>\n<\/tr>\n
237<\/td>\n13.2 Description <\/td>\n<\/tr>\n
238<\/td>\n13.3 Interfaces
13.3.1 Protocol data interface
13.3.1.1 Protocol configuration data
13.3.1.1.1 Host read and write access
13.3.1.1.2 Communication cycle timing configuration <\/td>\n<\/tr>\n
239<\/td>\n13.3.1.1.3 Protocol operation configuration <\/td>\n<\/tr>\n
240<\/td>\n13.3.1.1.4 Wakeup and startup configuration <\/td>\n<\/tr>\n
241<\/td>\n13.3.1.1.5 Network Management Vector configuration <\/td>\n<\/tr>\n
242<\/td>\n13.3.1.2 Protocol control data
13.3.1.2.1 Control of the protocol operation control
13.3.1.2.2 Control of MTS and WUDOP transmission <\/td>\n<\/tr>\n
244<\/td>\n13.3.1.2.3 Control of external clock synchronisation
13.3.1.3 Protocol status data
13.3.1.3.1 Overview and general behaviour
13.3.1.3.2 Protocol operation control status <\/td>\n<\/tr>\n
245<\/td>\n13.3.1.3.3 Wakeup and startup status
13.3.1.3.4 Communication cycle timing status <\/td>\n<\/tr>\n
246<\/td>\n13.3.1.3.5 Synchronisation frame status
13.3.1.3.6 Startup frame status <\/td>\n<\/tr>\n
247<\/td>\n13.3.1.3.7 Symbol window status
13.3.1.3.8 NIT status <\/td>\n<\/tr>\n
248<\/td>\n13.3.1.3.9 Aggregated channel status <\/td>\n<\/tr>\n
249<\/td>\n13.3.1.3.10 Dynamic segment status
13.3.2 Message data interface
13.3.2.1 Subject
13.3.2.2 Communication slot assignment <\/td>\n<\/tr>\n
250<\/td>\n13.3.2.3 Communication slot assignment for transmission
13.3.2.3.1 General behaviour
13.3.2.3.2 Cycle-independent and cycle-dependent slot assignment <\/td>\n<\/tr>\n
251<\/td>\n13.3.2.3.3 Transmission slot assignment list
13.3.2.3.4 Key slot assignment
13.3.2.4 Communication slot assignment for reception <\/td>\n<\/tr>\n
252<\/td>\n13.3.2.5 Conflicting communication slot assignment for reception and transmission
13.3.2.6 Non-queued message buffers
13.3.2.6.1 Structure and general behaviour
13.3.2.6.2 Message buffer configuration data <\/td>\n<\/tr>\n
254<\/td>\n13.3.2.6.3 Message buffer status data
13.3.2.6.4 Message buffer payload data and payload data valid flag <\/td>\n<\/tr>\n
255<\/td>\n13.3.2.6.5 Buffer enabling and buffer locking
13.3.2.7 Non-queued message buffer identification
13.3.2.7.1 Principles of message buffer selection <\/td>\n<\/tr>\n
256<\/td>\n13.3.2.7.2 Candidate transmit message buffer identification <\/td>\n<\/tr>\n
257<\/td>\n13.3.2.7.3 Candidate receive message buffer identification
13.3.2.7.4 Selected transmit buffer identification <\/td>\n<\/tr>\n
258<\/td>\n13.3.2.7.5 Selected receive buffer identification
13.3.2.7.6 Active message buffer identification
13.3.2.8 Message transmission
13.3.2.8.1 General concept
13.3.2.8.2 Transmit buffer configuration <\/td>\n<\/tr>\n
260<\/td>\n13.3.2.8.3 Transmit buffer identification for message retrieval
13.3.2.8.4 Transmit buffer status <\/td>\n<\/tr>\n
261<\/td>\n13.3.2.9 Message reception
13.3.2.9.1 Receive buffer types <\/td>\n<\/tr>\n
262<\/td>\n13.3.2.9.2 Non-queued receive buffer configuration <\/td>\n<\/tr>\n
263<\/td>\n13.3.2.9.3 Non-queued receive buffer contents
13.3.2.9.3.1 Slot status data <\/td>\n<\/tr>\n
265<\/td>\n13.3.2.9.3.2 Frame contents data <\/td>\n<\/tr>\n
266<\/td>\n13.3.2.10 Non-queued message buffer status update <\/td>\n<\/tr>\n
267<\/td>\n13.3.2.11 General concept
13.3.2.11.1 The concept of queued receive buffers
13.3.2.11.2 Basic FIFO behaviour
13.3.2.11.2.1 Design of a FIFO buffer <\/td>\n<\/tr>\n
269<\/td>\n13.3.2.11.2.2 Admittance into a FIFO <\/td>\n<\/tr>\n
270<\/td>\n13.3.2.11.2.3 Reading and removal from a FIFO
13.3.2.11.3 FIFO admittance criteria
13.3.2.11.3.1 Overview <\/td>\n<\/tr>\n
271<\/td>\n13.3.2.11.3.2 FIFO frame validity admittance criteria
13.3.2.11.3.3 FIFO channel admittance criteria
13.3.2.11.3.4 FIFO frame identifier admittance criteria <\/td>\n<\/tr>\n
272<\/td>\n13.3.2.11.3.5 FIFO cycle counter admittance criteria
13.3.2.11.3.6 Message identifier admittance criteria <\/td>\n<\/tr>\n
273<\/td>\n13.3.2.11.4 FIFO performance requirements <\/td>\n<\/tr>\n
274<\/td>\n13.3.2.11.5 FIFO status information <\/td>\n<\/tr>\n
275<\/td>\n13.3.3 CHI Services
13.3.3.1 Macrotick timer service
13.3.3.2 Interrupt service <\/td>\n<\/tr>\n
276<\/td>\n13.3.3.3 Message ID filtering service
13.3.3.4 Network management service <\/td>\n<\/tr>\n
363<\/td>\nBlank Page <\/td>\n<\/tr>\n
364<\/td>\nBlank Page <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Road vehicles. FlexRay communications system – Data link layer specification<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
BSI<\/b><\/a><\/td>\n2013<\/td>\n366<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":257865,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[742,2641],"product_tag":[],"class_list":{"0":"post-257863","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-43-040-15","7":"product_cat-bsi","9":"first","10":"instock","11":"sold-individually","12":"shipping-taxable","13":"purchasable","14":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/257863","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/257865"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=257863"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=257863"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=257863"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}