{"id":81489,"date":"2024-10-17T18:55:15","date_gmt":"2024-10-17T18:55:15","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1505-1-2008\/"},"modified":"2024-10-24T19:46:55","modified_gmt":"2024-10-24T19:46:55","slug":"ieee-1505-1-2008","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1505-1-2008\/","title":{"rendered":"IEEE 1505.1 2008"},"content":{"rendered":"
New IEEE Standard – Active. This trial-use standard represents an extension to the IEEE 1505 receiver fixture interface (RFI) standard specification. Particular emphasis is placed on defining within the IEEE 1505 RFI standard a more specific set of performance requirements that employ a common scalable: (a) pin map configuration; (b) specific connector modules; (c) respective contacts; (d)recommended switching implementation; and (e) legacy automatic test equipment (ATE)transitional devices. This is intentionally done to standardize the footprint and assure mechanical and electrical Interoperability between past and future automatic test systems (ATS).<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
1<\/td>\n | IEEE Std 1505.1\u2122-2008 <\/td>\n<\/tr>\n | ||||||
3<\/td>\n | Title page \n <\/td>\n<\/tr>\n | ||||||
6<\/td>\n | Introduction \n Notice to users \n Laws and regulations \n Copyrights \n <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | Updating of IEEE documents \n Errata \n Interpretations \n Patents \n <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | Participants \n <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | Contents \n <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | Important notice \n 1. Overview 1.1 Scope <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 1.2 Purpose 1.3 Statement of the problem <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 2. Normative references <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 3. Definitions, acronyms, and abbreviations 3.1 Definitions 3.2 Specification terms 3.3 Acronyms and abbreviations <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | 4. Common test interface requirements 4.1 Introduction 4.2 CTI open system requirements <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 4.3 CTI cost requirements 4.4 Vertical integration test support requirements <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | 4.5 CTI configuration\/interoperability requirements 4.6 Maintainability\/end-user support requirements 4.7 Scaleable architecture requirements <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | 4.8 Physical framework requirements <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 4.9 Reliability requirements <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | 4.10 CTI connector footprint\/parametric requirements <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | 4.11 CTI pin map requirements <\/td>\n<\/tr>\n | ||||||
43<\/td>\n | 4.12 CTI pin map input\/output configuration <\/td>\n<\/tr>\n | ||||||
44<\/td>\n | Annex A (normative) Common test interface signal definitions for pin map A.1 Analog instruments (AI) <\/td>\n<\/tr>\n | ||||||
46<\/td>\n | A.2 Bus <\/td>\n<\/tr>\n | ||||||
47<\/td>\n | A.3 Digital A.4 Instrument control A.5 Power loads <\/td>\n<\/tr>\n | ||||||
48<\/td>\n | A.6 Power supplies A.7 Sense and control, DCPS, and loads <\/td>\n<\/tr>\n | ||||||
49<\/td>\n | A.8 Switch <\/td>\n<\/tr>\n | ||||||
50<\/td>\n | A.9 System <\/td>\n<\/tr>\n | ||||||
169<\/td>\n | Annex B (informative) Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" IEEE Trial-Use Standard for the Common Test Interface Pin Map Configuration for High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505<\/b><\/p>\n |