{"id":79706,"date":"2024-10-17T18:37:07","date_gmt":"2024-10-17T18:37:07","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1076-2002\/"},"modified":"2024-10-24T19:41:02","modified_gmt":"2024-10-24T19:41:02","slug":"ieee-1076-2002","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1076-2002\/","title":{"rendered":"IEEE 1076 2002"},"content":{"rendered":"

Revision Standard – Inactive – Superseded. Replaced by 61691-1-1 Dual-logo document. Revision of the IEEE Std 1076, 2000 Edition Abstract: VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
10<\/td>\n0. Overview of this standard
0.1 Intent and scope of this standard
0.2 Structure and terminology of this standard <\/td>\n<\/tr>\n
14<\/td>\n1. Design entities and configurations
1.1 Entity declarations <\/td>\n<\/tr>\n
18<\/td>\n1.2 Architecture bodies <\/td>\n<\/tr>\n
21<\/td>\n1.3 Configuration declarations <\/td>\n<\/tr>\n
28<\/td>\n2. Subprograms and packages
2.1 Subprogram declarations <\/td>\n<\/tr>\n
31<\/td>\n2.2 Subprogram bodies <\/td>\n<\/tr>\n
34<\/td>\n2.3 Subprogram overloading <\/td>\n<\/tr>\n
36<\/td>\n2.4 Resolution functions <\/td>\n<\/tr>\n
37<\/td>\n2.5 Package declarations <\/td>\n<\/tr>\n
38<\/td>\n2.6 Package bodies <\/td>\n<\/tr>\n
40<\/td>\n2.7 Conformance rules <\/td>\n<\/tr>\n
42<\/td>\n3. Types <\/td>\n<\/tr>\n
43<\/td>\n3.1 Scalar types <\/td>\n<\/tr>\n
49<\/td>\n3.2 Composite types <\/td>\n<\/tr>\n
54<\/td>\n3.3 Access types <\/td>\n<\/tr>\n
57<\/td>\n3.4 File types <\/td>\n<\/tr>\n
59<\/td>\n3.5 Protected types <\/td>\n<\/tr>\n
64<\/td>\n4. Declarations
4.1 Type declarations <\/td>\n<\/tr>\n
65<\/td>\n4.2 Subtype declarations <\/td>\n<\/tr>\n
66<\/td>\n4.3 Objects <\/td>\n<\/tr>\n
80<\/td>\n4.4 Attribute declarations <\/td>\n<\/tr>\n
81<\/td>\n4.5 Component declarations
4.6 Group template declarations <\/td>\n<\/tr>\n
82<\/td>\n4.7 Group declarations <\/td>\n<\/tr>\n
84<\/td>\n5. Specifications
5.1 Attribute specification <\/td>\n<\/tr>\n
86<\/td>\n5.2 Configuration specification <\/td>\n<\/tr>\n
94<\/td>\n5.3 Disconnection specification <\/td>\n<\/tr>\n
98<\/td>\n6. Names
6.1 Names <\/td>\n<\/tr>\n
99<\/td>\n6.2 Simple names <\/td>\n<\/tr>\n
100<\/td>\n6.3 Selected names <\/td>\n<\/tr>\n
102<\/td>\n6.4 Indexed names <\/td>\n<\/tr>\n
103<\/td>\n6.5 Slice names
6.6 Attribute names <\/td>\n<\/tr>\n
106<\/td>\n7. Expressions
7.1 Expressions <\/td>\n<\/tr>\n
107<\/td>\n7.2 Operators <\/td>\n<\/tr>\n
115<\/td>\n7.3 Operands <\/td>\n<\/tr>\n
122<\/td>\n7.4 Static expressions <\/td>\n<\/tr>\n
124<\/td>\n7.5 Universal expressions <\/td>\n<\/tr>\n
126<\/td>\n8. Sequential statements
8.1 Wait statement <\/td>\n<\/tr>\n
128<\/td>\n8.2 Assertion statement <\/td>\n<\/tr>\n
129<\/td>\n8.3 Report statement
8.4 Signal assignment statement <\/td>\n<\/tr>\n
134<\/td>\n8.5 Variable assignment statement <\/td>\n<\/tr>\n
135<\/td>\n8.6 Procedure call statement <\/td>\n<\/tr>\n
136<\/td>\n8.7 If statement
8.8 Case statement <\/td>\n<\/tr>\n
137<\/td>\n8.9 Loop statement <\/td>\n<\/tr>\n
138<\/td>\n8.10 Next statement <\/td>\n<\/tr>\n
139<\/td>\n8.11 Exit statement
8.12 Return statement
8.13 Null statement <\/td>\n<\/tr>\n
142<\/td>\n9. Concurrent statements
9.1 Block statement <\/td>\n<\/tr>\n
143<\/td>\n9.2 Process statement <\/td>\n<\/tr>\n
144<\/td>\n9.3 Concurrent procedure call statements <\/td>\n<\/tr>\n
145<\/td>\n9.4 Concurrent assertion statements <\/td>\n<\/tr>\n
146<\/td>\n9.5 Concurrent signal assignment statements <\/td>\n<\/tr>\n
151<\/td>\n9.6 Component instantiation statements <\/td>\n<\/tr>\n
157<\/td>\n9.7 Generate statements <\/td>\n<\/tr>\n
158<\/td>\n10. Scope and visibility
10.1 Declarative region <\/td>\n<\/tr>\n
159<\/td>\n10.2 Scope of declarations <\/td>\n<\/tr>\n
160<\/td>\n10.3 Visibility <\/td>\n<\/tr>\n
163<\/td>\n10.4 Use clauses <\/td>\n<\/tr>\n
164<\/td>\n10.5 The context of overload resolution <\/td>\n<\/tr>\n
166<\/td>\n11. Design units and their analysis
11.1 Design units
11.2 Design libraries <\/td>\n<\/tr>\n
167<\/td>\n11.3 Context clauses <\/td>\n<\/tr>\n
168<\/td>\n11.4 Order of analysis <\/td>\n<\/tr>\n
170<\/td>\n12. Elaboration and execution
12.1 Elaboration of a design hierarchy <\/td>\n<\/tr>\n
172<\/td>\n12.2 Elaboration of a block header <\/td>\n<\/tr>\n
173<\/td>\n12.3 Elaboration of a declarative part <\/td>\n<\/tr>\n
177<\/td>\n12.4 Elaboration of a statement part <\/td>\n<\/tr>\n
180<\/td>\n12.5 Dynamic elaboration
12.6 Execution of a model <\/td>\n<\/tr>\n
188<\/td>\n13. Lexical elements
13.1 Character set <\/td>\n<\/tr>\n
191<\/td>\n13.2 Lexical elements, separators, and delimiters <\/td>\n<\/tr>\n
192<\/td>\n13.3 Identifiers
13.4 Abstract literals <\/td>\n<\/tr>\n
194<\/td>\n13.5 Character literals
13.6 String literals <\/td>\n<\/tr>\n
195<\/td>\n13.7 Bit string literals <\/td>\n<\/tr>\n
196<\/td>\n13.8 Comments <\/td>\n<\/tr>\n
197<\/td>\n13.9 Reserved words <\/td>\n<\/tr>\n
198<\/td>\n13.10 Allowable replacements of characters <\/td>\n<\/tr>\n
200<\/td>\n14. Predefined language environment
14.1 Predefined attributes <\/td>\n<\/tr>\n
214<\/td>\n14.2 Package STANDARD <\/td>\n<\/tr>\n
221<\/td>\n14.3 Package TEXTIO <\/td>\n<\/tr>\n
226<\/td>\nAnnex A (informative)
\nSyntax summary <\/td>\n<\/tr>\n
246<\/td>\nAnnex B (informative)
\nGlossary <\/td>\n<\/tr>\n
266<\/td>\nAnnex C (informative) Potentially nonportable constructs <\/td>\n<\/tr>\n
268<\/td>\nAnnex D (informative)
\nChanges from IEEE Std 1076,2000 Edition <\/td>\n<\/tr>\n
270<\/td>\nAnnex E (informative)
\nFeatures under consideration for removal <\/td>\n<\/tr>\n
272<\/td>\nAnnex F (informative)
\nBibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard VHDL Language Reference Manual<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2002<\/td>\n309<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":79707,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-79706","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/79706","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/79707"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=79706"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=79706"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=79706"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}