This part of the IEC 62647 series defines for circuit card assemblies (CCA):<\/p>\n
a default method for those companies that require a pre-defined approach, and<\/p>\n<\/li>\n
a protocol for those companies that wish to develop their own test methods.<\/p>\n<\/li>\n<\/ul>\n
The intent of this document is not to prescribe a certain method, but to aid avionics\/defence suppliers in satisfying the reliability and\/or performance requirements of IEC\/TS 62647-1 as well as support the expectations in IEC\/TS 62647-21.<\/p>\n
The default method (see Clause 5) is intended for use by electronic equipment manufacturers, repair facilities, or programs that, for a variety of reasons, may be unable to develop methods specific to their own products and applications. It should be used when little or no other information is available to define, conduct, and interpret results from reliability, qualification, or other tests for electronic equipment containing lead-free (Pb-free) solder. The default method is intended to be conservative, i.e., it is biased toward minimizing the risk to users of ADHP electronic equipment.<\/p>\n
The protocol (see Clause 6) is intended for use by manufacturers or repair facilities that have the necessary resources to design and conduct reliability, qualification, or process development tests that are specific to their products, their operating conditions, and their applications. Users of the protocol will have the necessary knowledge, experience, and data to customize their own methods for designing, conducting, and interpreting results from the data. Key to developing a protocol is a firm understanding of all material properties for the lead-free (Pb-free) material in question as well as knowledge of package- and board-level attributes as described in 5.3.2. As an example, research has shown that the mechanisms for creep can be different between tin-lead and tin-silver-copper (SAC) solders. Understanding these mechanisms is key to determining critical test parameters such as dwell time for thermal cycling. The protocol portion of this document provides guidance on performing sufficient characterization of new materials in order to accurately define test parameters.<\/p>\n
Use of the protocol is encouraged, since it is likely to yield more accurate results, and to be less expensive than the default method. The IEC\/TS 62647-22 provides a comprehensive overview of those technical considerations necessary in implementing a test protocol.<\/p>\n
This specification addresses the evaluation of failure mechanisms, through performance testing, expected in electronic products containing lead-free (Pb-free) solder. One failure mode, fatigue-failure through the solder-joint, is considered a primary failure mode in ADHP electronics and can be understood in terms of physics of failure and life-projections. Understanding all of the potential failure modes caused by lead-free (Pb-free) solder of ADHP electronics is a critical element in defining early field-failures\/reliability issues. Grouping of different failure modes may result in incorrect and\/or misleading test conclusions. Failure analysis efforts should be conducted to insure that individual failure modes are identified, thus enabling the correct application of reliability assessments and life-projection efforts.<\/p>\n
When properly used, the methods or protocol defined in this specification can be used along with the processes documented in compliance to the IPC-SM-785, to satisfy, at least in part, the reliability requirements of the IPC-SM-785 and JESD22-B110A.<\/p>\n
Any portion of this document can be used to develop a lead-free (Pb-free) assembly test program, i.e., this document is tailorable and provides room for flexibility. For those situations in which results are used for reliability, verification, or qualification, stakeholder concurrence needs to be sought and documented so that expectations are understood and addressed.<\/p>\n
This specification may be used for products in all stages of the transition to lead-free (Pbfree) solder, including:<\/p>\n
products that have been designed and qualified with traditional tin-lead electronic components, materials, and assembly processes, and are being re-qualified with use of lead-free (Pb-free) components;<\/p>\n<\/li>\n
products with tin-lead designs transitioning to lead-free (Pb-free) solder; and<\/p>\n<\/li>\n
products newly-designed with lead-free (Pb-free) solder.<\/p>\n<\/li>\n<\/ul>\n
For programs that were designed with tin-lead solder, and are currently not using any leadfree (Pb-free) solder, the traditional methods may be used. It is important, however, for those programs to have processes in place to maintain the tin-lead configuration including those outsourced or manufactured by subcontractors.<\/p>\n
With respect to products as mentioned above, the methods presented in this document are intended to be applied at the level of assembly at which soldering occurs, i.e., circuit card assembly (CCA) level.<\/p>\n
This document may be used by other high-performance and high-reliability industries, at their discretion.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 4<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
| 6<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 8<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | 1 Scope <\/td>\n<\/tr>\n | ||||||
| 11<\/td>\n | 2 Normative references 3 Terms, definitions and abbreviations 3.1 Terms and definitions <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | 3.2 Abbreviations <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | 4 Assumption 5 Default test methods 5.1 General 5.2 Test vehicles 5.2.1 Test vehicle type <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | 5.2.2 Sample size 5.3 Pre-conditioning by thermal aging method 5.3.1 General 5.3.2 Thermal aging acceleration model <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | 5.3.3 Default test parameters 5.4 Default temperature cycle test method 5.4.1 Test parameters 5.4.2 Test duration 5.4.3 Failure determination and analysis <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | 5.4.4 Acceleration model <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | 5.5 Vibration test <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | 5.6 Mechanical shock 5.7 Combined environments 6 Protocol to design and conduct performance tests 6.1 General <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | 6.2 Test vehicles 6.3 Temperature cycle test protocol 6.3.1 General 6.3.2 Measure the recovery time <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | 6.3.3 Determine the high-temperature dwell times and temperatures Figures Figure 1 \u2013 Notional method for determining the recovery time for a given solder alloy, or combination of alloys <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | 6.3.4 Select other test parameters as appropriate for the application 6.3.5 Conduct tests 6.3.6 Determine the temperature versus cycles-to-failure relationship Figure 2 \u2013 Notional method for determining the relationship between high temperature dwell time, thd, and recovery time, tr <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | 6.3.7 Estimate the cycles-to-failure 6.4 Vibration test Figure 3 \u2013 Cycles-to-failure \u2013 Notional method for determining the relationship between cycles-to-failure <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | 6.5 Mechanical shock 6.6 Combined environments test protocol <\/td>\n<\/tr>\n | ||||||
| 26<\/td>\n | 6.7 Failure determination and analysis 7 Final remarks <\/td>\n<\/tr>\n | ||||||
| 27<\/td>\n | Annex A (informative) Test sample size <\/td>\n<\/tr>\n | ||||||
| 29<\/td>\n | Annex B (informative) Material properties of lead-free solder materials <\/td>\n<\/tr>\n | ||||||
| 30<\/td>\n | Tables Table B.1 \u2013 Test and acceleration model parameters <\/td>\n<\/tr>\n | ||||||
| 33<\/td>\n | Annex C (informative) NASA-DoD lead-free electronics project test information C.1 General C.2 Vibration test C.2.1 General C.2.2 Vibration test description <\/td>\n<\/tr>\n | ||||||
| 34<\/td>\n | Figure C.1 \u2013 Vibration spectrum Table C.1 \u2013 Vibration profile <\/td>\n<\/tr>\n | ||||||
| 35<\/td>\n | C.2.3 Vibration test rationale <\/td>\n<\/tr>\n | ||||||
| 36<\/td>\n | C.2.4 Vibration of major or unique equipment Figure C.2 \u2013 Vibration test fixture Table C.2 \u2013 Vibration test methodology <\/td>\n<\/tr>\n | ||||||
| 37<\/td>\n | C.2.5 Vibration data recording and calculations C.3 Mechanical shock C.3.1 Mechanical shock description Figure C.3 \u2013 Vibration table showing Y-axis <\/td>\n<\/tr>\n | ||||||
| 38<\/td>\n | C.3.2 Mechanical shock rationale Figure C.4 \u2013 Mechanical shock response spectrum <\/td>\n<\/tr>\n | ||||||
| 39<\/td>\n | C.3.3 Mechanical shock of major or unique equipment Table C.3 \u2013 Mechanical shock test methodology \u2013 Test procedure <\/td>\n<\/tr>\n | ||||||
| 40<\/td>\n | C.3.4 Data recording and calculations C.4 Combined environment test C.4.1 General Figure C.5 \u2013 Mechanical shock test set-up <\/td>\n<\/tr>\n | ||||||
| 41<\/td>\n | C.4.2 Combined environment test description C.4.3 Combined environment test rationale Table C.4 \u2013 Combined environments test methodology <\/td>\n<\/tr>\n | ||||||
| 42<\/td>\n | C.4.4 Data recording and calculations <\/td>\n<\/tr>\n | ||||||
| 43<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Process management for avionics. Aerospace and defence electronic systems containing lead-free solder – Performance testing for systems containing lead-free solder and finishes<\/b><\/p>\n |