This part of IEC 62878 describes the design guide of device embedded substrates.<\/p>\n
The design guide of device embedded substrate is essentially the same as that of various electronic circuit boards. This part of IEC 62878 enables a thorough understanding of circuit design, structure design, board design, board manufacturing, jisso (assembly processes) and tests of products.<\/p>\n
This part of IEC 62878 is applicable to device embedded substrates fabricated by use of organic base material, which include for example active or passive devices, discrete components formed in the fabrication process of electronic wiring board, and sheet formed components.<\/p>\n
The IEC 62878 series neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as an M-type business model in IEC 62421.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 4<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
| 6<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 8<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
| 9<\/td>\n | 1 Scope 2 Normative references 3 Terms, definition and abbreviations 3.1 Terms and definitions 3.2 Abbreviations <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | 4 Structure of device embedded substrates 4.1 General 4.2 Specification of the top and bottom surfaces of a device embedded substrate Figures Figure 1 \u2013 Definition of top and bottom surfaces of a device embedded substrate <\/td>\n<\/tr>\n | ||||||
| 11<\/td>\n | 4.3 Definition of layers of a device embedded substrate Figure 2 \u2013 Definition of top and bottom surfaces for mounting on a mother board Figure 3 \u2013 Names of layers in pad connection <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | Figure 4 \u2013 Additional information concerning the interconnection position <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | Figure 5 \u2013 Names of layers in via connection [I] Figure 6 \u2013 Names of layers in via connection [II] <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | 4.4 Conductor spacing at a terminal Figure 7 \u2013 Names of layers in via connection [III] Tables Table 1 \u2013 Name of layers of device embedded board <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | Figure 8 \u2013 Definitions of dielectric gap and layer gap in the pad connection method Figure 9 \u2013 Definitions of dielectric gap and layer gap in the via connection method <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | Figure 10 \u2013 Additional illustration of dielectric gap Figure 11 \u2013 Additional illustration of layer gap <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | 5 Conditions to prepare base and embedding devices 5.1 Conditions for base Table 2 \u2013 Recommendation for device assembly to base substrate for device embedded boards <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | 5.2 Conditions for embedding devices Table 3 \u2013 Embedding recommendation <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | Table 4 \u2013 Mounting methods of semiconductor devices <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | 6 Recommendation for embedding devices Table 5 \u2013 Embedding device <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | 7 Design specification of device embedded substrate 7.1 General 7.2 Items to be included in the design specification 7.2.1 Graphical indication of device embedding substrate Figure 12 \u2013 Additional drawing <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | 7.2.2 Design specification template Figure 13 \u2013 Forbidden wiring area <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | Table 6 \u2013 Specification of device embedded substrate 1 <\/td>\n<\/tr>\n | ||||||
| 24<\/td>\n | Table 7 \u2013 Specification of device embedded substrate 2 <\/td>\n<\/tr>\n | ||||||
| 25<\/td>\n | Table 8 \u2013 Specification of device embedded substrate 3 <\/td>\n<\/tr>\n | ||||||
| 26<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Device embedded substrate – Guidelines. Design guide<\/b><\/p>\n |