{"id":385779,"date":"2024-10-20T03:32:19","date_gmt":"2024-10-20T03:32:19","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-iso-21111-62021\/"},"modified":"2024-10-26T06:26:19","modified_gmt":"2024-10-26T06:26:19","slug":"bs-iso-21111-62021","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-iso-21111-62021\/","title":{"rendered":"BS ISO 21111-6:2021"},"content":{"rendered":"<p>This document specifies advanced features of an <span class=\"std\"> <span class=\"std-ref\">ISO\/IEC\/IEEE&nbsp;8802-3<\/span><\/span> automotive Ethernet PHY (often also called transceiver), e.g. for diagnostic purposes for automotive Ethernet PHYs.<\/p>\n<p>This document specifies:<\/p>\n<ul>\n<li>\n<p>advanced PHY features;<\/p>\n<\/li>\n<li>\n<p>wake-up and sleep features;<\/p>\n<\/li>\n<li>\n<p>PHY test suite;<\/p>\n<\/li>\n<li>\n<p>PHY control IUT requirements and conformance test plan;<\/p>\n<\/li>\n<li>\n<p>PCS test suite;<\/p>\n<\/li>\n<li>\n<p>PCS IUT requirements and conformance test plan;<\/p>\n<\/li>\n<li>\n<p>PMA test suite; and<\/p>\n<\/li>\n<li>\n<p>PMA IUT requirements and conformance test plan.<\/p>\n<\/li>\n<\/ul>\n<h4>PDF Catalog<\/h4>\n<table border=\"1px\" class=\"des-table\">\n<tr>\n<th>PDF Pages<\/th>\n<th>PDF Title<\/th>\n<\/tr>\n<tr>\n<td><b>2<b><\/td>\n<td>undefined  <\/td>\n<\/tr>\n<tr>\n<td><b>7<b><\/td>\n<td>Foreword   <\/td>\n<\/tr>\n<tr>\n<td><b>8<b><\/td>\n<td>Introduction   <\/td>\n<\/tr>\n<tr>\n<td><b>10<b><\/td>\n<td>1 Scope  <br \/> 2 Normative references  <br \/> 3 Terms and definitions   <\/td>\n<\/tr>\n<tr>\n<td><b>11<b><\/td>\n<td>4 Symbols and abbreviated terms  <br \/> 4.1 Symbols  <br \/> 4.2 Abbreviated terms   <\/td>\n<\/tr>\n<tr>\n<td><b>13<b><\/td>\n<td>5 Conventions  <br \/> 6 Wake-up and sleep features  <br \/> 6.1 Extension of physical coding sub-layer   <\/td>\n<\/tr>\n<tr>\n<td><b>15<b><\/td>\n<td>6.2 Service primitives and interfaces   <\/td>\n<\/tr>\n<tr>\n<td><b>16<b><\/td>\n<td>6.3 Power sequencing states   <\/td>\n<\/tr>\n<tr>\n<td><b>17<b><\/td>\n<td>6.4 Command definitions  <br \/> 6.4.1 General  <br \/> 6.4.2 Low power sleep (LPS)   <\/td>\n<\/tr>\n<tr>\n<td><b>18<b><\/td>\n<td>6.4.3 Wake-up request (WUR)  <br \/> 6.4.4 Wake-up pulse (WUP)  <br \/> 6.5 Generation of scrambling bits Sdn[2:0]   <\/td>\n<\/tr>\n<tr>\n<td><b>19<b><\/td>\n<td>6.6 PCS PHY control state diagram   <\/td>\n<\/tr>\n<tr>\n<td><b>21<b><\/td>\n<td>7 CTP test system and CTC structure  <br \/> 7.1 General   <\/td>\n<\/tr>\n<tr>\n<td><b>22<b><\/td>\n<td>7.2 Test system set-up \u2013 Transmit test system   <\/td>\n<\/tr>\n<tr>\n<td><b>23<b><\/td>\n<td>7.3 Test system set-up \u2013 Receive test system   <\/td>\n<\/tr>\n<tr>\n<td><b>24<b><\/td>\n<td>7.4 CTC structure   <\/td>\n<\/tr>\n<tr>\n<td><b>25<b><\/td>\n<td>8 PHY \u2013 Control IUT conformance test plan (with MII access)  <br \/> 8.1 PHY \u2013 Group 1: PHY control and timers (with MII access)  <br \/> 8.1.1 Overview  <br \/> 8.1.2 CTC_4.1.1 \u2013 PMA reset (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>26<b><\/td>\n<td>8.1.3 CTC_4.1.2 \u2013 Value of minwait_timer \u2013 minwait_timer in TRAINING state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>30<b><\/td>\n<td>8.1.4 CTC_4.1.3 \u2013 Value of maxwait_timer (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>31<b><\/td>\n<td>8.1.5 CTC_4.1.4 \u2013 Value of stabilize_timer (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>32<b><\/td>\n<td>8.2 PHY \u2013 Group 2: PHY control state diagram (with MII access)  <br \/> 8.2.1 Overview  <br \/> 8.2.2 CTC_4.2.1 \u2013 PHY control state diagram &#8211; DISABLE TRANSMITTER state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>33<b><\/td>\n<td>8.2.3 CTC_4.2.2 \u2013 PHY control state diagram &#8211; SLAVE SILENT state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>34<b><\/td>\n<td>8.2.4 CTC_4.2.3 \u2013 PHY control state diagram \u2013 TRAINING state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>37<b><\/td>\n<td>8.2.5 CTC_4.2.4 \u2013 PHY control state diagram \u2013 SEND IDLE state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>40<b><\/td>\n<td>8.2.6 CTC_4.2.5 \u2013 PHY control state diagram \u2013 SEND IDLE OR DATA state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>44<b><\/td>\n<td>8.3 PHY \u2013 Group 3: PHY link monitor state diagram (with MII access)  <br \/> 8.3.1 Overview   <\/td>\n<\/tr>\n<tr>\n<td><b>45<b><\/td>\n<td>8.3.2 CTC_4.3.1 \u2013 Link monitor state diagram \u2013 IUT does not enter the LINK OK state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>47<b><\/td>\n<td>9 PCS \u2013 IUT conformance test plan (with MII access)  <br \/> 9.1 PCS \u2013 Group 1: PCS transmit (with MII access)  <br \/> 9.1.1 Overview   <\/td>\n<\/tr>\n<tr>\n<td><b>48<b><\/td>\n<td>9.1.2 CTC_3.1.1 \u2013 PCS signalling (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>50<b><\/td>\n<td>9.1.3 CTC_3.1.2 \u2013 PCS reset (with MII access)  <br \/> 9.1.4 CTC_3.1.3 \u2013 PCS transmit proper SSD (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>51<b><\/td>\n<td>9.1.5 CTC_3.1.4 \u2013 PCS transmit proper ESD (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>52<b><\/td>\n<td>9.1.6 CTC_3.1.5 \u2013 PCS transmit ESD with tx_error (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>53<b><\/td>\n<td>9.1.7 CTC_3.1.6 \u2013 PCS transmission of stuff bits (with MII access)  <br \/> 9.1.8 CTC_3.1.7 \u2013 PCS tx_error (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>55<b><\/td>\n<td>9.2 PCS \u2013 Group 2: PCS transmit state diagram (with MII access)  <br \/> 9.2.1 Overview  <br \/> 9.2.2 CTC_3.2.1 \u2013 PCS transmit state diagram &#8211; SEND IDLE state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>56<b><\/td>\n<td>9.2.3 CTC_3.2.2 \u2013 PCS transmit state diagram &#8211; SSD1 VECTOR and SSD2 VECTOR states (with MII access)  <br \/> 9.2.4 CTC_3.2.3 \u2013 PCS transmit state diagram &#8211; SSD3 VECTOR state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>58<b><\/td>\n<td>9.2.5 CTC_3.2.4 \u2013 PCS transmit state diagram &#8211; TRANSMIT DATA state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>59<b><\/td>\n<td>9.2.6 CTC_3.2.5 \u2013 PCS transmit state diagram &#8211; ESD1 VECTOR state (with MII access)  <br \/> 9.2.7 CTC_3.2.6 \u2013 PCS transmit state diagram &#8211; ESD2 VECTOR state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>60<b><\/td>\n<td>9.2.8 CTC_3.2.7 \u2013 PCS transmit state diagram &#8211; ESD3 VECTOR state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>61<b><\/td>\n<td>9.2.9 CTC_3.2.8 \u2013 PCS transmit state diagram &#8211; ERR ESD1 VECTOR state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>62<b><\/td>\n<td>9.2.10 CTC_3.2.9 \u2013 PCS transmit state diagram &#8211; ERR ESD2 VECTOR state (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>63<b><\/td>\n<td>9.2.11 CTC_3.2.10 \u2013 PCS transmit state diagram &#8211; ERR ESD3 VECTOR state (with MII access)  <br \/> 9.3 PCS \u2013 Group 3: PCS receive (with MII access)  <br \/> 9.3.1 Overview  <br \/> 9.3.2 CTC_3.3.1 \u2013 PCS receive signalling (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>64<b><\/td>\n<td>9.3.3 CTC_3.3.2 \u2013 PCS automatic polarity detection (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>65<b><\/td>\n<td>9.3.4 CTC_3.3.3 \u2013 PCS receive SSD (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>66<b><\/td>\n<td>9.3.5 CTC_3.3.4 \u2013 PCS receive ESD (with MII access)  <br \/> 9.3.6 CTC_3.3.5 \u2013 PCS receive ERR ESD3 (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>67<b><\/td>\n<td>9.3.7 CTC_3.3.6 \u2013 PCS reception of stuff bits (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>68<b><\/td>\n<td>9.3.8 CTC_3.3.7 \u2013 PCS de-interleave ternary pairs (with MII access)  <br \/> 9.4 PCS \u2013 Group 4: PCS receive state diagram (with MII access)  <br \/> 9.4.1 Overview  <br \/> 9.4.2 CTC_3.4.1 \u2013 PCS receive state diagram (with MII access) &#8211; IDLE state   <\/td>\n<\/tr>\n<tr>\n<td><b>69<b><\/td>\n<td>9.4.3 CTC_3.4.2 \u2013 PCS receive state diagram (with MII access) &#8211; CHECK SSD2 state   <\/td>\n<\/tr>\n<tr>\n<td><b>70<b><\/td>\n<td>9.4.4 CTC_3.4.3 \u2013 PCS receive state diagram (with MII access) &#8211; CHECK SSD3 state  <br \/> 9.4.5 CTC_3.4.4 \u2013 PCS receive state diagram (with MII access) &#8211; SSD state   <\/td>\n<\/tr>\n<tr>\n<td><b>71<b><\/td>\n<td>9.4.6 CTC_3.4.5 \u2013 PCS receive state diagram (with MII access) &#8211; BAD SSD state   <\/td>\n<\/tr>\n<tr>\n<td><b>72<b><\/td>\n<td>9.4.7 CTC_3.4.6 \u2013 PCS receive state diagram (with MII access) &#8211; FIRST SSD state   <\/td>\n<\/tr>\n<tr>\n<td><b>73<b><\/td>\n<td>9.4.8 CTC_3.4.7 \u2013 PCS receive state diagram (with MII access) &#8211; SECOND SSD state   <\/td>\n<\/tr>\n<tr>\n<td><b>74<b><\/td>\n<td>9.4.9 CTC_3.4.8 \u2013 PCS receive state diagram (with MII access) &#8211; THIRD SSD state  <br \/> 9.4.10 CTC_3.4.9 \u2013 PCS receive state diagram (with MII access) &#8211; DATA state   <\/td>\n<\/tr>\n<tr>\n<td><b>75<b><\/td>\n<td>9.4.11 CTC_3.4.10 \u2013 PCS receive state diagram (with MII access) &#8211; CHECK ESD2 state   <\/td>\n<\/tr>\n<tr>\n<td><b>76<b><\/td>\n<td>9.4.12 CTC_3.4.11 \u2013 PCS receive state diagram (with MII access) &#8211; CHECK ESD3 state   <\/td>\n<\/tr>\n<tr>\n<td><b>77<b><\/td>\n<td>9.4.13 CTC_3.4.12 \u2013 PCS receive state diagram (with MII access) \u2013 BAD ESD2 state   <\/td>\n<\/tr>\n<tr>\n<td><b>78<b><\/td>\n<td>9.4.14 CTC_3.4.13 \u2013 PCS receive state diagram (with MII access) &#8211; BAD END and RX ERROR states   <\/td>\n<\/tr>\n<tr>\n<td><b>79<b><\/td>\n<td>9.5 PCS \u2013 Group 5: PCS JAB state diagram (with MII access)  <br \/> 9.5.1 Overview  <br \/> 9.5.2 CTC_3.5.1 \u2013 PCS JAB state diagram (with MII access) &#8211; rcv_max_timer   <\/td>\n<\/tr>\n<tr>\n<td><b>80<b><\/td>\n<td>10 PMA \u2013 IUT requirements and conformance test plan (with MII access)  <br \/> 10.1 PMA \u2013 Group 1: PMA electrical measurements (with MII access)  <br \/> 10.1.1 Overview  <br \/> 10.1.2 CTC_5.1.1 \u2013 PMA maximum transmitter output droop (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>81<b><\/td>\n<td>10.1.3 CTC_5.1.2 \u2013 PMA transmitter distortion (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>82<b><\/td>\n<td>10.1.4 CTC_5.1.3 \u2013 PMA transmitter timing jitter (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>83<b><\/td>\n<td>10.1.5 CTC_5.1.4 \u2013 PMA transmitter power spectral density (PSD) (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>85<b><\/td>\n<td>10.1.6 CTC_5.1.5 \u2013 PMA transmit clock frequency (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>86<b><\/td>\n<td>10.1.7 CTC_5.1.6 \u2013 PMA MDI return loss (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>88<b><\/td>\n<td>10.1.8 CTC_5.1.7 \u2013 PMA MDI mode conversion loss (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>91<b><\/td>\n<td>10.1.9 CTC_5.1.8 \u2013 PMA transmitter peak differential output (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>92<b><\/td>\n<td>10.2 PMA \u2013 Group 2: PMA receive tests (with MII access)  <br \/> 10.2.1 Group 2 overview  <br \/> 10.2.2 CTC_5.2.1 \u2013 PMA bit error rate verification (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>93<b><\/td>\n<td>10.2.3 CTC_5.2.2 \u2013 PMA receiver frequency tolerance (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>94<b><\/td>\n<td>10.2.4 CTC_5.2.3 \u2013 PMA alien crosstalk noise rejection (with MII access)   <\/td>\n<\/tr>\n<tr>\n<td><b>96<b><\/td>\n<td>Annex A (informative) PHY control \u2013 Test suite   <\/td>\n<\/tr>\n<tr>\n<td><b>100<b><\/td>\n<td>Annex B (normative) PCS \u2013 Test suite   <\/td>\n<\/tr>\n<tr>\n<td><b>119<b><\/td>\n<td>Annex C (normative) PMA \u2013 Test system set-ups   <\/td>\n<\/tr>\n<tr>\n<td><b>132<b><\/td>\n<td>Bibliography   <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"<p><b>Road vehicles. In-vehicle Ethernet &#8211; Electrical 100-Mbit\/s physical entity requirements and conformance test plan<\/b><\/p>\n<table class=\"shortdes-table\" style=\"width: 100%\" border=\"0\" cellspacing=\"0\" cellpadding=\"0\">\n<tbody>\n<tr>\n<td>Published By<\/td>\n<td>Publication Date<\/td>\n<td>Number of Pages<\/td>\n<\/tr>\n<tr>\n<td><a href=\"https:\/\/pdfstandards.shop\/product-category\/publishers\/bsi\/\"><b>BSI<\/b><\/a><\/td>\n<td>2021<\/td>\n<td>134<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":385784,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[741,2641],"product_tag":[],"class_list":{"0":"post-385779","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-43-040-10","7":"product_cat-bsi","9":"first","10":"instock","11":"sold-individually","12":"shipping-taxable","13":"purchasable","14":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/385779","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/385784"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=385779"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=385779"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=385779"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}