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IEEE IEC 62050 2005

$141.92

IEC 62050 Ed. 1 (IEEE Std 1076.6(TM)-2004): IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

Published By Publication Date Number of Pages
IEEE 2005 128
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New IEEE Standard – Active. Replaces IEEE Std 1076.6-2004 / Dual logo standard This document specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.

PDF Catalog

PDF Pages PDF Title
1 Front Cover
4 CONTENTS
5 FOREWORD
8 IEEE Introduction
11 1. Overview
1.1 Scope
1.2 Compliance to this standard
12 1.3 Terminology
1.4 Conventions
13 2. References
3. Definitions and acronyms
3.1 Definitions
14 3.2 Acronyms
15 4. Predefined types
5. Verification methodology
16 5.1 Combinational verification
5.2 Sequential verification
17 6. Modeling hardware elements
6.1 Edge-sensitive sequential logic
29 6.2 Level-sensitive sequential logic
33 6.3 Three-state logic and busses
6.4 Combinational logic
34 6.5 ROM and RAM memories
39 7. Pragmas
7.1 Attributes
56 7.2 Metacomments
57 8. Syntax
8.1 Design entities and configurations
62 8.2 Subprograms and packages
66 8.3 Types
71 8.4 Declarations
77 8.5 Specifications
79 8.6 Names
81 8.7 Expressions
85 8.8 Sequential statements
91 8.9 Concurrent statements
96 8.10 Scope and visibility
97 8.11 Design units and their analysis
98 8.12 Elaboration
8.13 Lexical elements
8.14 Predefined language environment
101 Annex A (informative) Syntax summary
120 Annex B (normative) Synthesis package RTL_ATTRIBUTES
121 Annex C (informative) List of Participants
122 Index
IEEE IEC 62050 2005
$141.92