IEEE 1076.4-2000

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IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification

Published By	Publication Date	Number of Pages
IEEE	2000	429

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Description

Revision Standard – Inactive-Withdrawn. The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.

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PDF Pages	PDF Title
1	Cover Page
2	Title Page
4	Introduction
5	Participants
7	CONTENTS
10	1. Overview 1.1 Scope 1.2 Purpose 1.3 Intent of this standard 1.4 Structure and terminology of this standard
11	1.5 Syntactic description
12	1.6 Semantic description 1.7 Front matter, examples, figures, notes, and annexes 2. References
13	3. Basic elements of the VITAL ASIC modeling specification 3.1 VITAL modeling levels and compliance
14	3.2 VITAL standard packages 3.3 VITAL specification for timing data insertion
16	4. The Level 0 specification 4.1 The VITAL_Level0 attribute 4.2 General usage rules
17	4.3 The Level 0 entity interface
26	4.4 The Level 0 architecture body
28	5. Backannotation 5.1 Backannotation methods
29	5.2 The VITAL SDF map
44	6. The Level 1 specification 6.1 The VITAL_Level1 attribute 6.2 The Level 1 architecture body
45	6.3 The Level 1 architecture declarative part 6.4 The Level 1 architecture statement part
55	7. Predefined primitives and tables 7.1 VITAL logic primitives
57	7.2 VitalResolve 7.3 VITAL table primitives
63	8. Timing constraints 8.1 Timing check procedures
68	8.2 Modeling negative timing constraints
79	9. Delay selection 9.1 VITAL delay types and subtypes
80	9.2 Transition dependent delay selection 9.3 Glitch handling
81	9.4 Path delay procedures
83	9.5 Delay selection in VITAL primitives
84	9.6 VitalExtendToFillDelay
85	10. The Level 1 Memory specification 10.1 The VITAL Level 1 Memory attribute 10.2 The VITAL Level 1 Memory architecture body
86	10.3 The VITAL Level 1 Memory architecture declarative part 10.4 The VITAL Level 1 Memory architecture statement part
96	11. VITAL Memory function specification 11.1 VITAL memory construction
99	11.2 VITAL memory table specification
108	11.3 VitalDeclareMemory
110	11.4 VitalMemoryTable
112	11.5 VitalMemoryCrossPorts
114	11.6 VitalMemoryViolation
117	12. VITAL memory timing specification 12.1 VITAL memory timing types
118	12.2 Memory Output Retain timing behavior
119	12.3 VITAL Memory output retain timing specification 12.4 Transition dependent delay selection
120	12.5 VITAL memory path delay procedures
125	12.6 VITAL memory timing check procedures
130	13. The VITAL standard packages 13.1 VITAL_Timing package declaration
145	13.2 VITAL_Timing package body
172	13.3 VITAL_Primitives package declaration
241	13.4 VITAL_Primitives package body
311	13.5 VITAL_Memory package declaration
332	13.6 VITAL_Memory package body
421	Annex A (informative) Syntax summary
427	Annex B (informative) Glossary
429	Annex C (informative) Bibliography

Additional information

Standard Title	IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification
Published Code	IEEE
Publication Date	2000
Pages Count	429

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IEEE 1076.4-2000

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