BSI PD IEC/TR 62240-1:2018 – TC:2020 Edition
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Tracked Changes. Process management for avionics. Electronic components capability in operation – Temperature uprating
| Published By | Publication Date | Number of Pages |
| BSI | 2020 | 118 |
IEC TR 62240-1:2018 is available as /2 which contains the International Standard and its Redline version, showing all changes of the technical content compared to the previous edition. IEC TR 62240-1:2018 is a technical report, which provides information when using semiconductor devices in wider temperature ranges than those specified by the device manufacturer. The uprating solutions described herein are considered exceptions, when no reasonable alternatives are available; otherwise devices are utilized within the manufacturers’ specifications. This document describes the methods and processes for implementing this special case of thermal uprating. All of the elements of these methods and processes employ existing, commonly used best engineering practices. No new or unique engineering knowledge is needed to follow these processes, only a rigorous application of the overall approach. The terms “uprating” and “thermal uprating” are being used increasingly in avionics industry discussions and meetings, and clear definitions are included in the present IEC Technical Report. They were coined as shorthand references to a special case of methods commonly used in selecting electronic components for circuit design. This new edition cancels and replaces the first edition published in 2013 and includes a revised wording for subclause 4.1 (Introduction to selection provisions) and the associated flowchart.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 62 | undefined |
| 64 | CONTENTS |
| 67 | FOREWORD |
| 69 | INTRODUCTION |
| 70 | 1 Scope 2 Normative references 3 Terms, definitions and abbreviated terms 3.1 Terms and definitions |
| 74 | 3.2 Abbreviated terms 4 Selection provisions 4.1 General |
| 75 | Figures Figure 1 – Flow chart for semiconductor devices over wider temperature ranges |
| 76 | 4.2 Device selection, usage and alternatives 4.2.1 General 4.2.2 Alternatives 4.2.3 Device technology |
| 77 | 4.2.4 Compliance with the electronic component management plan 4.3 Device capability assessment 4.3.1 General 4.3.2 Device package and internal construction capability assessment 4.3.3 Risk assessment (assembly level) |
| 78 | 4.3.4 Device uprating methods |
| 79 | 4.3.5 Device reliability assurance |
| 80 | 4.4 Device quality assurance (QA) over wider temperature ranges 4.4.1 Decision for the optimum QA method |
| 81 | 4.4.2 Device level testing 4.4.3 Higher level assembly testing 4.5.1 General 4.5.2 Semiconductor device change monitoring |
| 82 | 4.6 Final electronic equipment assurance 4.7 Documentation and identification 4.7.1 Documentation 4.7.2 Device identification 4.7.3 Customer notification |
| 83 | Figure 2 – Report form for documenting device usage over wider temperature ranges |
| 84 | Annexes Annex A (informative) Device parameter re-characterisation A.1 Glossary of symbols |
| 85 | A.2 Rationale for parameter re-characterisation A.2.1 General A.2.2 Assessment for uprateability Figure A.1 – Parameter re-characterisation |
| 86 | A.3 Capability assurance A.3.1 Description A.3.2 Parameter re-characterisation process |
| 87 | Figure A.2 – Flow diagram of parameter re-characterisation capability assurance process |
| 88 | Tables Table A.1 – Example of sample size calculation |
| 90 | Figure A.3 – Margin in electrical parameter measurement based on the results of the sample test |
| 91 | A.3.3 Application capability assessment Figure A.4 – Schematic diagram of parameter limit modifications Table A.2 – Parameter re-characterisation example: SN74ALS244 octal buffer/driver |
| 92 | A.4 Quality assurance A.5 Factors to be considered in parameter re-characterisation Figure A.5 – Parameter re-characterisation device quality assurance |
| 93 | Figure A.6 – Schematic of outlier products that can invalidate sample testing |
| 94 | A.6 Report form for documenting device parameter re-characterisation Figure A.7 – Example of intermediate peak of an electrical parameter: Voltage feedback input threshold change for Motorola MC34261 power factor controller, see [4] |
| 95 | Figure A.8 – Report form for documenting device parameter re-characterisation |
| 96 | Annex B (informative) Stress balancing B.1 General B.2 Glossary of symbols B.3 Stress balancing B.3.1 General |
| 97 | B.3.2 Determine the ambient temperature extremes B.3.3 Determine parameter relationship to power dissipation B.3.4 Determine the dissipated power versus ambient temperature relationship |
| 98 | Figure B.1 – Iso-TJ curve: Relationship between ambient temperature and dissipated power |
| 99 | B.3.5 Assess applicability of the method B.3.6 Determine the new parameter values |
| 100 | B.3.7 Conduct parametric and functional tests B.4 Application example B.4.1 General Figure B.2 – Graph of electrical parameters versus dissipated power |
| 101 | B.4.2 Determine the ambient temperature extremes B.4.3 Select the parameters that can be derated |
| 102 | B.4.4 Construct an Iso-TJ plot B.4.5 Determine whether or not the device can be uprated B.4.6 Determine the new parameter values Figure B.3 – Iso-TJ curve for the Fairchild MM74HC244 |
| 103 | B.4.7 Conduct parametric and functional tests B.5 Other notes B.5.1 Margins B.5.2 Cautions and limitations Figure B.4 – Power versus frequency curve for the Fairchild MM74HC244 |
| 104 | Figure B.5 – Flow chart for stress balancing |
| 105 | Figure B.6 – Report form for documenting stress balancing |
| 106 | Annex C (informative) Parameter conformance assessment C.1 General C.2 Test plan C.2.1 General C.2.2 Critical parameters C.2.3 Minimum allowable test margins |
| 107 | C.2.4 Test options Figure C.1 – Relationship of temperature ratings, requirements and margins |
| 109 | Figure C.2 – Typical fallout distribution versus Treq-max |
| 110 | C.2.5 Quality assurance |
| 111 | Figure C.3 – Parameter conformance assessment flow |
| 112 | Figure C.4 – Report form for documenting parameter conformance testing |
| 113 | Annex D (informative) Higher assembly level testing D.1 General D.2 Process D.2.1 General D.2.2 Analysis of assembly test definition D.2.3 Perform assembly test |
| 114 | D.2.4 Document results D.2.5 Maintenance notification Figure D.1 – Flow chart of higher level assembly testing |
| 115 | Figure D.2 – Report form for documenting higherlevel assembly test at temperature extremes |
| 116 | Bibliography |
