BS ISO 21806-11:2021
$215.11
Road vehicles. Media Oriented Systems Transport (MOST) – 150-Mbit/s coaxial physical layer conformance test plan
Published By | Publication Date | Number of Pages |
BSI | 2021 | 96 |
This document specifies the conformance test plan for the 150-Mbit/s coaxial physical layer for MOST (MOST150 cPHY), a synchronous time-division-multiplexing network.
This document specifies the basic conformance test measurement methods, relevant for verifying compatibility of networks, nodes, and MOST components with the requirements specified in ISO 21806-10.
PDF Catalog
PDF Pages | PDF Title |
---|---|
2 | National foreword |
7 | Foreword |
8 | Introduction |
11 | 1 Scope 2 Normative references 3 Terms and definitions |
12 | 4 Symbols and abbreviated terms 4.1 Symbols 4.2 Abbreviated terms |
13 | 5 Conventions |
14 | 6 Operating conditions and measurement tools, requested accuracy 6.1 Operating conditions 6.2 Apparatus — Measurement tools, requested accuracy 6.2.1 Oscilloscope 6.2.2 VNA or TDR (TDR bandwidth ≥ 3,5 GHz). 6.2.3 Ampere meter 7 Electrical characteristics 7.1 Test according to LVDS |
15 | 7.2 Test according to LVTTL 8 Coaxial characteristics 8.1 High/low detection at SP2 8.2 Transition times at SP2 |
16 | 8.3 Steady state amplitude at SP2 8.4 Attenuation of coaxial interconnect 8.4.1 General |
17 | 8.4.2 Coefficient values based on attenuation measurements 8.4.3 Fitting of corridor 8.4.4 Attenuation test set-up |
18 | 8.4.5 Test procedure |
23 | 8.5 RL of connectors and couplers 8.6 Characteristic impedance of coaxial cable 8.7 RL of coaxial interconnect |
25 | 8.8 RL of PCB interfaces |
26 | 8.9 Stimulus creation for SP3 8.9.1 General 8.9.2 Pattern generator |
27 | 8.9.3 Arbitrary signal generator 8.9.4 Attenuator 8.9.5 Cable or analogue representation |
28 | 8.9.6 Noise generator 8.9.7 Creating a stimulus for SP3 for simplex applications |
30 | 8.9.8 Creating a stimulus for SP3 for duplex applications |
34 | 9 Measurement of phase variation 9.1 General |
35 | 9.2 Measuring alignment jitter |
38 | 9.3 Measuring transferred jitter |
40 | 10 Test set-ups 10.1 General |
41 | 10.2 Graphical symbols and descriptions 10.2.1 Pattern generator SP1 10.2.2 SP3 stimulus 10.2.3 Standalone simplex ECport under test |
42 | 10.2.4 Integrated simplex ECport under test 10.2.5 Standalone simplex CEport under test |
43 | 10.2.6 Integrated simplex CEport under test 10.2.7 Duplex ECport under test |
44 | 10.2.8 Duplex CEport under test |
45 | 10.3 Set-ups for dual simplex 10.3.1 General 10.3.2 SP2 signal quality measurement for simplex |
46 | 10.3.3 SP4 jitter measurement (AJ and TJ) for simplex |
48 | 10.4 Set-ups for duplex 10.4.1 General 10.4.2 Directional couplers |
50 | 10.4.3 SP2 signal quality measurement for duplex |
52 | 10.4.4 SP4 jitter measurement (AJ and TJ) for duplex |
54 | 11 Power-on and power-off 11.1 General |
55 | 11.2 Measuring ECC parameters 11.2.1 Measuring ECC parameters – Test set-up |
56 | 11.2.2 Measuring ECC parameters – Signal charts |
57 | 11.2.3 Measuring ECC parameters – Test sequences |
61 | 11.3 Measuring CEC parameters 11.3.1 Measuring CEC parameters – Test set-up |
63 | 11.3.2 Measuring CEC parameters – Signal charts 11.3.3 Measuring CEC parameters – Test sequences |
67 | 12 Detecting bit rate (frequency reference) 13 System performance 13.1 General 13.2 SP4 receiver tolerance |
68 | 13.3 TimingMaster delay tolerance |
71 | 14 Conformance tests of 150-Mbit/s coaxial physical layer 14.1 Location of interfaces |
74 | 14.2 Control signals |
75 | 14.3 Limited access to specification points |
76 | 14.4 Parameter overview 15 Limited physical layer conformance 15.1 Overview |
77 | 15.2 Test set-ups 1 and 2 |
78 | 15.3 Generating test signals for the IUT input section SP3 |
79 | 15.4 Analysis of test results 15.5 Test flow overview |
80 | 15.6 Measurement of SP3 input signal of the IUT |
81 | 15.7 Measurement of SP2 output signal of the IUT |
82 | 15.8 Measurement of RL 15.9 Functional test of wake-up and shutdown 16 Direct physical measuring accuracy |
83 | 17 Measurement of Port1 delay drift |
84 | Annex A (informative) Limited physical layer conformance for development tools |
85 | Annex B (normative) SP3 stress conditions |
86 | Annex C (normative) Compensation set-up for MOST150 cPHY duplex |
90 | Annex D (informative) Test procedure for 2-port nodes |
94 | Bibliography |