IEEE 2977-2021

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IEEE Standard for Adoption of MIPI Alliance Specification for A-PHY Interface (A-PHY) Version 1.0

Published By	Publication Date	Number of Pages
IEEE	2021

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Description

New IEEE Standard – Active. This standard adopts MIPI Alliance–MIPI A-PHY Specification Version 1.0 as an IEEE Standard. The adopted standard provides an asymmetric data link in a point-to-point or daisy-chain topology, with high-speed unidirectional data, embedded bidirectional control data and optional power delivery over a single cable. In this way, it reduces wiring, cost and weight, as high-speed data, control data and optional power share the same physical wiring. For integration with existing network backbones, it complements Ethernet, Controller Area Network (CAN), FlexRay, and other interfaces.

PDF Catalog

PDF Pages	PDF Title
1	Front Cover
2	Title page
4	Notice and Disclaimer of Liability Concerning the Use of IEEE Standards Documents
8	Participants
9	Introduction
10	Specification for A-PHY Contents
16	Figures
20	Tables
24	Release History
26	1 Introduction 1.1 Scope 1.1.1 In Scope 1.1.2 Out of Scope 1.2 Purpose
27	2.1 Use of Special Terms 2.2 Definitions
28	2.3 Abbreviations
29	2.4 Acronyms
31	3 References
33	4 Overview
35	5 Architecture 5.1 High Level Structure
36	5.2 Profiles
37	5.3 Gears
38	5.4 Safety
40	6 Interconnect 6.1 Lane Configuration 6.2 Cable Topology
41	6.3 Boundary Conditions 6.4 S-Parameter Specifications 6.5 Characterization Conditions
42	6.6 Interconnect Specifications
43	6.6.1 Total Interconnect 6.6.2 Cable TLIS (Transmission Line Interconnect Structure) 6.6.2.1 Characteristic Impedance 6.6.2.2 Insertion Loss
44	6.6.2.3 Return Loss
45	6.6.2.4 Coupling Attenuation
47	6.6.2.5 Alien Cable Bundle Crosstalk
48	6.6.3 ENIS (End Node Interconnect Structure) 6.6.3.1 Characteristic Impedance
49	6.6.3.2 Insertion Loss
50	6.6.3.3 Return Loss
51	6.6.3.4 Mode Conversion 6.6.3.5 Receiver Alien Near End Crosstalk
52	6.6.4 PCB TLIS (Transmission Line Interconnect Structure) (Informative)
53	6.6.4.1 Characteristic Impedance 6.6.4.2 Insertion Loss 6.6.4.3 Return Loss 6.6.5 Power Distribution 6.6.5.1 DC Requirements
54	6.6.5.2 AC Requirements
55	6.6.5.3 Power Over Coax 6.6.5.4 Power Over Differential Line
56	6.6.6 Ground Voltage Offset
57	7 EMC Environmental Conditions 7.1 RF Ingress 7.2 Bulk Current Injection (BCI)
58	7.3 Fast Transient 7.4 Alien Cable Bundle Max PSD Level
59	7.5 Car Noise (PSD)
60	8 PHY Layer 8.1 Architecture 8.1.1 High Level Structure 8.1.2 Port Specification Generalization
61	8.1.3 Master/Slave Clocking Schemes 8.1.4 PHY Layer Implementation Guidelines 8.1.4.1 A-PHY P1 G1/G2 Architecture
62	8.1.4.2 A-PHY P2 G1/G2 Architecture
63	8.1.4.3 A-PHY G3–G5 Architecture
65	8.1.5 PHY-Related A-Packet Fields 8.2 RTS
70	8.2.1 PAM-X Payload Data Modulation Assignment by Source
71	8.2.2 Active Message Counter Window Informative Implementation Note 8.2.3 Retransmission Request / Ack Types
72	Informative Note 8.2.3.1 Retransmission Request Triggering by the Receiver
73	Example: Recurrent, Unsatisfied Retransmission, Request Generation (Informative) 8.2.3.2 Retransmission Request Handling at TX RTS 8.2.3.3 Format of Single/Gap Retransmission Request Sent Over Downlink
75	8.2.4 Time Bounded RTS
76	8.2.5 A-Packet – PHY Related Header/Tail Modifications 8.2.5.1 Tx Delay 8.2.5.2 Message Counter and Original Indication Bit 8.2.5.3 Header CRC (CRC-8)
78	8.2.5.4 A-Packet Tail CRC (CRC-32)
79	8.2.6 Fully Paced A-Packet Stream from TX Data Link Layer to TX RTS 8.2.6.1 Max Net Link Rate for 8B/10B PCS 8.2.6.2 Max Net Link Rate for PAM-X PCS 8.2.6.3 8B/10B PCS Fully Paced, A-Packets Stream from Link to TX RTS
80	8.2.6.4 PAM-X PCS Fully Paced, A-Packets Stream from Link to TX RTS
81	PAM-X Pacing Implementation Example (Informative) 8.2.7 Retransmitted A-Packets Scheduling Priority at TX RTS 8.2.8 RTS Bypass
83	8.3 Physical Coding Sub-Layer (PCS) 8.3.1 PAM-X PCS
84	8.3.1.1 PAM16 Sub-Constellation Bit to Symbol mapping
86	8.3.1.2 Symbol and Token Rate/Period
88	8.3.1.3 A-Packet to Token Conversion
90	8.3.1.4 Downlink Scrambler
91	8.3.1.5 Downlink Training Mode
93	8.3.1.5.1 Mode Transition from Training to Idle
94	8.3.1.6 Downlink Idle Mode 8.3.1.7 Downlink Normal Mode
96	8.3.1.8 Downlink JITC Re-Training
97	8.3.2 8B/10B PCS
98	8.3.2.1 10b Symbols to NRZ Mapping 8.3.2.2 8B/10B Encoding 8.3.2.3 Uplink Scrambler
99	8.3.2.4 Downlink Scrambler 8.3.2.5 Byte Stream Controller 8.3.2.5.1 Data Bytes 8.3.2.5.2 Control Byte 8.3.2.5.3 Startup Control Sequence
100	8.3.2.5.4 Normal Control Sequence 8.3.2.6 Training Mode
101	8.3.2.7 Idle Mode
102	8.3.2.8 Normal Mode 8.3.2.8.1 Re-Train Request
103	8.3.2.8.2 sCMax Request 8.3.2.8.3 Single Retransmission Request 8.3.2.8.4 Retransmission Gap Request
104	8.3.2.8.5 Ack Indication 8.3.2.8.6 Data Packet
105	8.3.3 Startup Procedure
106	8.3.3.1 “Mission Mode” Startup Procedure
108	8.3.3.2 Unidirectional Startup Procedure
111	9 PMD Electrical Specification 9.1 TX Electrical Specification 9.1.1 Test Mode Pattern Generator (TMPG)
112	9.1.1.1 LFSR Usage Example
114	9.1.2 Test Modes 9.1.2.1 TM1: Test Mode 1: Transmit PSD 9.1.2.2 TM2: Test Mode 2: Droop
115	9.1.2.3 TM3: Test Mode 3: Transmit Jitter 9.1.2.4 TM4: Test Mode 4: Transmit Linearity 9.1.2.5 TM5: Test Mode 5: In Silent State 9.1.2.6 TM6: Test Mode 6: Unidirectional Startup 9.1.3 Transmitter Power Spectral Density Mask 9.1.3.1 Requirement
116	9.1.3.1.1 NRZ PMD PSD Limits
117	9.1.3.1.2 Uplink PMD PSD Limits
118	9.1.3.1.3 PAM-X PMD PSD Limits
119	9.1.3.2 Processing Procedure 9.1.3.2.1 Matlab Example Code (Informative)
123	9.1.4 Transmitter Maximum Output Droop 9.1.4.1 Requirement 9.1.4.2 Processing Procedure 9.1.5 Transmitter Timing Jitter 9.1.5.1 Requirement 9.1.5.2 Processing Procedure
124	9.1.6 Transmitter Symbol Rate Accuracy 9.1.7 NRZ Downlink Transmitter Eye Opening 9.1.7.1 Requirement 9.1.7.2 Processing Procedure
125	9.1.7.3 NRZ Jitter (Informative)
126	9.1.8 PAM-X Transmitter Linearity 9.1.8.1 Requirement 9.1.8.2 Processing Procedure
127	9.1.8.2.1 Matlab Example Code (Informative)
129	9.2 RX Electrical Specification 9.2.1 Profile 1 Receiver Bit Error Rate 9.2.2 Profile 2 Downlink Receiver Pre-RTS Packet Error Rate 9.2.3 Profile 2 Uplink Receiver Bit Error Rate 9.2.4 Receiver Symbol Rate Frequency Tolerance 9.2.5 Receiver Test Modes 9.2.5.1 RTM6: Receiver Test Mode 6: Unidirectional Startup
131	10 Modes of Operation 10.1 Non-Active Mode 10.2 Active Mode 10.3 Operation Mode State Machine
132	10.3.1 General Operation 10.3.2 States
133	10.3.2.1 Power-Up State 10.3.2.2 Start-Up State 10.3.2.3 Normal State 10.3.2.4 Sleep State
134	10.3.3 Transitions 10.3.3.1 Power-Off Transition 10.3.3.2 Reset Transition 10.3.3.3 Ready Transition 10.3.3.4 Stop Transition
135	10.3.3.5 Link Establish Transition 10.3.3.6 Link Down Transition 10.3.3.7 Sleep Transition
136	10.3.3.8 Wakeup Transition 10.3.4 Test Mode
137	10.4 FSM Parameters
138	10.5 Wake-Up Protocol 10.5.1 General 10.5.1.1 System Architecture (Informative)
141	10.5.2 Wake-Up Pattern (WUP) Signal 10.5.2.1 PRBS9 Pattern 10.5.2.2 WUP Amplitude
142	10.5.2.3 WUP Bit Rate 10.5.2.4 WUP Duration 10.5.2.5 WUP Generation 10.5.2.6 WUP Detection 10.5.3 WUP Handshake Procedure
143	10.5.4 WUP Parameters
144	11 Data Link Layer 11.1 Architecture Overview
146	11.2 A-Packet Format
147	11.2.1 A-Packet Header (A-Header) Fields
148	11.2.1.1 Adaptation Descriptor Field 11.2.1.1.1 Adaptation Type Sub-Field 11.2.1.2 Service Descriptor Field 11.2.1.2.1 PHY1 Sub-Field 11.2.1.2.2 Prio Sub-Field
149	11.2.1.2.3 QoS Sub-Field 11.2.1.2.4 BAD Sub-Field
151	11.2.1.3 Placement Descriptor Field 11.2.1.3.1 ALEI (Adaptation Layer Extended Info) Sub-Field 11.2.1.3.2 OB (Odd-Bytes) Sub-Field 11.2.1.3.3 Order Sub-Field 11.2.1.4 PHY2 Field 11.2.1.5 Target Address Field
153	11.2.1.6 PHY3 Field 11.2.1.7 Payload Length Field 11.2.1.8 PHY Header CRC Field 11.2.2 A-Packet Payload (A-Payload) 11.2.3 A-Packet Tail (A-Tail) (CRC-32 Field)
154	11.3 Link Service 11.3.1 BIST A-Packet 11.3.1.1 BIST Modes 11.3.1.2 BIST Payload Patterns 11.3.1.3 BIST Rate
155	11.3.1.4 BIST Burst 11.3.2 Keep-Alive 11.3.3 Remote Sleep Command
156	11.4 Local Functions 11.4.1 Local Table (LOC_TBL) Recommendations (Informative)
158	11.5 Multi-Port Functions
159	11.5.1 Multi-Port Routing Function 11.5.1.1 Packet Duplication Stage 11.5.1.2 Packet Forwarding Stage
160	11.5.1.3 Routing Table (ROUT_TBL) Recommendations (Informative) 11.5.1.4 Duplication Table (DUP_TBL) Recommendations (Informative)
162	11.6 Network Functions 11.6.1 Scheduling and Priorities 11.6.2 Clock Forwarding Service 11.6.2.1 CFS A-Packet Format
163	11.6.2.1.1 Frequency Offset (FreqOffset) Field 11.6.2.1.2 Adaptation Layer Type (AL_Type) Field 11.6.2.1.3 Measurement Field 11.6.2.1.4 Accumulated Delay (ACC_DELAY) Field 11.7 APPI Signal Interface
164	11.7.1 Signals Description 11.7.1.1 APPI Signals
165	11.7.2 APPI Clock
166	11.7.3 APPI A-Packet Mapping 11.7.4 APPI Timing Diagrams
169	12 A-PHY Control and Management Database (ACMD) and Protocol (ACMP)
170	12.1 Control and Management System Architecture (Informative)
171	12.2 ACMD 12.2.1 Register Base Address Alignment 12.2.2 Register Data Byte Order
172	12.2.3 Register Space
173	12.2.4 Register List
175	12.2.5 Detailed Register Description 12.2.5.1 ACMD Programming
179	12.2.5.2 Port Programming
185	12.3 ACMP
186	12.3.1 ACMP Message Format 12.3.1.1 ACMP Message Header Part
187	12.3.1.1.1 Header CRC (HCRC) Field 12.3.1.2 ACMP Message Payload Part
188	12.3.1.2.1 Payload CRC (PCRC)
189	12.3.1.3 ACMP Message Mapping to I2C
190	12.3.2 ACMP Message Receiver Rules and Responsibilities 12.3.2.1 ACMP Header CRC (HCRC) Errors 12.3.2.2 ACMP Payload CRC (PCRC) Errors 12.3.2.3 Message Counter (MC) 12.3.2.4 Keep-Alive 12.3.2.5 Message Format Setting 12.3.2.6 Virtual Base Address Maintenance 12.3.2.7 Accessing Register Data 12.3.3 ACMP Interrupts
191	12.3.3.1 ACMPI in I2C 12.3.3.2 ACMPI in I3C
192	Annex A PMD Simplified Implementation Examples (Informative)
196	Participants
198	Annex B (informative) Exerpt from Specification for M-PHY®
205	Back Cover